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usb audio mcu HT82A824R revision: v1.00 date: ??? i? 1?? ? 011 ???i? 1?? ? 011
rev 1.00 ? ???i? 1?? ? 011 rev 1.00 3 ???i? 1?? ? 011 HT82A824R usb audio mcu table of contents eates cpu featu?es .......................................................................................................................... 7 gene?a? desc?i?tion .......................................................................................... 8 b?ock diag?am ................................................................................................... 8 pin ?ssignment ................................................................................................. 9 pin desc?i?tion ................................................................................................. 9 ?bso?ute maximum ratings ........................................................................... 10 d.c. cha?acte?istics ........................................................................................ 11 ?.c. cha?acte?istics ........................................................................................ 1? system ??chitectu?ex ..................................................................................... 1? c?ocking and pi?e?ining .......................................................................................................... 1? p?og?am counte? .................................................................................................................... 13 stack ...................................................................................................................................... 1? ??ithmetic and logic unit C ?lu ............................................................................................ 15 p?og?am memo?y ............................................................................................ 15 o?ganisation ........................................................................................................................... 15 s?ecia? vecto?s ...................................................................................................................... 15 look-u? tab?e ......................................................................................................................... 17 tab ?e p?og?am exam??e ......................................................................................................... 18 data memo?y ................................................................................................... 19 o?ganisation ........................................................................................................................... 19 gene?a? pu??ose data memo?y ............................................................................................. ?0 s?ecia? pu??ose data memo?y .............................................................................................. ?0 s?ecia? function registe?s ............................................................................ ?1 indi?ect add?essing ?egiste? C i?r0? i?r1 .............................................................................. ?1 memo?y pointe? C mp0? mp1 ................................................................................................. ?1 bank pointe? C bp .................................................................................................................. ?? ?ccumu?ato? C ?cc ............................................................................................................... ?? p?og?am counte? low registe? C pcl ................................................................................... ?? look-u? tab? e registe? s C tblp ? tblh? tbhp ..................................................................... ?3 watchdog time ? registe? C wdts ....................................................................................... ?3 status registe? C st ? tus ..................................................................................................... ?3 inte??u?t cont?o? registe?s C intc0? intc1? mfi1c ............................................................. ?? time ?/event counte? registe? s C tmrl/tmrh? tmrc ........................................................ ?? in?ut/out?ut po?ts and cont?o? registe?s .............................................................................. ?? po?t ? wake-u ? cont?o? registe? C p ?_w ?ke_ctrl ........................................................... ?5 pu?se width modu?ato? registe?s C pwm0? pwm1? pwmc .................................................. ?5 ? /d conve?te? registe? s C ?drl? ?drh? ?dcr? ?csr ....................................................... ?5 usb registe?s ........................................................................................................................ ?5 pfd registe?s C pfdc? pfdd .............................................................................................. ?5
rev 1.00 ? ???i? 1?? ? 011 rev 1.00 3 ???i? 1?? ? 011 HT82A824R usb audio mcu othe? registe?s ..................................................................................................................... ?5 input/output ports .......................................................................................... 26 pu??-high resisto?s ................................................................................................................. ?6 po? t wake-u? ......................................................................................................................... ?6 i/o po?t cont?o? registe?s ...................................................................................................... ?7 pin-sha?ed functions ............................................................................................................. ?7 i/o pin st?uctu?es ................................................................................................................... ?8 p?og?amming conside?ations ................................................................................................. ?9 timer/event counters .................................................................................... 29 confguring the timer/event counter input clock source ..................................................... 30 time ? registe? s C tmr0h/tmr0l? tmr1l/tmr1h .............................................................. 30 time ? cont?o? registe? C tmr0c? tmr1c ............................................................................ 31 confguring the timer mode ................................................................................................... 31 confguring the event counter mode ..................................................................................... 3? confguring the pulse width measurement mode .................................................................. 3? i/o inte?facing ......................................................................................................................... 33 p?og?amming conside?ations ................................................................................................. 3? time ? p?og?am exam??e ........................................................................................................ 35 p?og?ammab?e f?equency divide? C pfd .............................................................................. 35 power amplifer ............................................................................................... 37 p?og?ammab?e ?ttenuato? ...................................................................................................... 37 ? tten_ctrl_l and ? tten_ctrl_r registe?s ................................................................. 37 interrupts ......................................................................................................... 38 inte??u?t registe?s .................................................................................................................. 38 inte??u?t o?e?ation ................................................................................................................. 38 inte??u?t p?io?ity ...................................................................................................................... 39 usb inte??u?t ......................................................................................................................... ?1 time ?/event counte? inte??u?t ................................................................................................ ?1 p?ay inte??u?t .......................................................................................................................... ?1 mu?ti function inte??u?t .......................................................................................................... ?? exte?na? inte??u?t .................................................................................................................... ?3 ?/d conve?te? inte??u?t .......................................................................................................... ?3 se?ia? inte?face inte??u?t ......................................................................................................... ?3 p?og?amming conside?ations ................................................................................................. ?? reset and initialisation ................................................................................... 44 reset functions ..................................................................................................................... ?? reset initia? conditions .......................................................................................................... ?7 oscillator ......................................................................................................... 50 system c?ysta?/ce?amic osci??ato? ......................................................................................... 50 watchdog time ? osci??ato? ..................................................................................................... 50 power down mode and wake-up ................................................................... 51 powe? down mode ................................................................................................................. 51 ente?ing the powe? down mode ............................................................................................ 51
rev 1.00 ? ???i? 1?? ? 011 rev 1.00 5 ???i? 1?? ? 011 HT82A824R usb audio mcu standby cu??ent conside?ations ............................................................................................ 51 wake-u ? ................................................................................................................................. 5? watchdog timer .............................................................................................. 53 usb function .................................................................................................. 55 usb inte?face ......................................................................................................................... 55 usb inte?face registe?s ......................................................................................................... 55 usc registe? ......................................................................................................................... 55 usr registe? ......................................................................................................................... 57 ucc registe? ........................................................................................................................ 58 ? wr registe? ......................................................................................................................... 59 st ? ll registe? ..................................................................................................................... 59 sies registe? ......................................................................................................................... 60 misc registe? ....................................................................................................................... 6? setio registe? ...................................................................................................................... 63 usb_st ? te registe? ............................................................................................................ 6? sus? end wake-u? remote wake-u? .................................................................................... 65 usf registe? .......................................................................................................................... 65 ?udio data fo?mat ................................................................................................................. 69 usb s?eake? vo?ume cont?o? ................................................................................................ 70 fifo registe?s ....................................................................................................................... 70 d?c limit registe?s ............................................................................................................... 71 spi serial interface ......................................................................................... 72 spi inte?face communication ................................................................................................ 7? spi registe?s ......................................................................................................................... 7? spi bus enab?e/disab?e ......................................................................................................... 73 spi o?e?ation ......................................................................................................................... 73 e??o? detection ....................................................................................................................... 76 p?og?amming conside?ations ................................................................................................. 76 mode cont?o? registe? ........................................................................................................... 76 p?ay data ................................................................................................................................ 78 analog to digital converter ........................................................................... 78 ?/d ove?view ......................................................................................................................... 78 ?/d conve?te? data registe?s C ?drl? ?drh ...................................................................... 78 ?/d conve?te? cont?o? registe? C ?dcr ............................................................................... 79 ?/d conve?te? c?ock sou?ce registe? C ?csr ...................................................................... 80 ?/d in?ut pins ........................................................................................................................ 80 initia?ising the ?/d conve?te? .................................................................................................. 81 summa?y of ?/d conve?sion ste?s ........................................................................................ 81 p?og?amming conside?ations ................................................................................................. 8? ?/d p?og?amming exam??e .................................................................................................... 8? ?/d t ?ansfe? function ............................................................................................................ 85 uart bus serial interface ............................................................................. 85 u? rt featu?es ...................................................................................................................... 85
rev 1.00 ? ???i? 1?? ? 011 rev 1.00 5 ???i? 1?? ? 011 HT82A824R usb audio mcu u? rt exte?na? pin inte?facing ............................................................................................... 86 u? rt data t ?ansfe? scheme ................................................................................................. 86 u? rt status and cont?o? registe?s ....................................................................................... 86 usr1 registe? ....................................................................................................................... 87 ucr1 registe? ....................................................................................................................... 89 ucr? registe? ....................................................................................................................... 90 baud rate gene?ato? ............................................................................................................. 9? ca?cu?ating the registe? and e??o? va?ues ............................................................................. 9? setting up and controlling the uart ........................................................... 93 int?oduction ............................................................................................................................ 93 enab?ing/disab?ing the u? rt ................................................................................................. 93 data? pa?ity and sto? bit se?ection ........................................................................................ 9? u? rt t ?ansmitte? ................................................................................................................... 9? t ?ansmitting data ................................................................................................................... 9? t ?ansmit b?eak ....................................................................................................................... 95 uart receiver ................................................................................................ 96 int?oduction ............................................................................................................................ 96 receiving data ....................................................................................................................... 96 receive b?eak ........................................................................................................................ 97 id?e status .............................................................................................................................. 97 receive? inte??u?t ................................................................................................................... 97 managing receive? e??o?s ..................................................................................................... 97 ove??un e??o? C oerr f?ag ................................................................................................... 97 noise e??o? C nf f?ag ............................................................................................................ 98 f?aming e??o? C ferr f?ag ................................................................................................... 98 pa?ity e??o? C perr f?ag ....................................................................................................... 98 ua?t inte??u?t scheme ............................................................................................................ 98 ?dd?ess detect mode ............................................................................................................. 99 ua?t o?e?ation in powe? down mode .................................................................................. 100 pulse width modulator ................................................................................. 100 6+? pwm mode ................................................................................................................... 101 7+1 pwm mode ................................................................................................................... 10? pwm out?ut cont?o? ............................................................................................................ 103 confguration options .................................................................................. 104 application circuits ...................................................................................... 105 instruction set ............................................................................................... 106 int?oduction .......................................................................................................................... 106 inst? uction timing ................................................................................................................. 106 moving and t ?ansfe??ing data .............................................................................................. 106 ??ithmetic o?e?ations ........................................................................................................... 106 logica? and rotate o?e?ations ............................................................................................. 106 b?anches and cont?o? t ?ansfe? ............................................................................................ 107 bit o?e?ations ...................................................................................................................... 107
rev 1.00 6 ???i? 1?? ? 011 rev 1.00 7 ???i? 1?? ? 011 HT82A824R usb audio mcu tab ?e read o?e?ations ........................................................................................................ 107 othe? o?e?ations .................................................................................................................. 107 instruction set summary ............................................................................. 108 tab ?e conventions ................................................................................................................ 108 instruction defnition .................................................................................... 110 package information .................................................................................... 120 ?8-? in lqfp (7mmx7mm) out?ine dimensions ................................................................... 1?0
rev 1.00 6 ???i? 1?? ? 011 rev 1.00 7 ???i? 1?? ? 011 HT82A824R usb audio mcu features cpu features usb 2.0 full speed compatible usb spec v1.1 full speed operation and usb audio device class spec v1.0 operating voltage at f sys = 6m/12mhz: 4.0v~5.5v 48khz/44.1khz sampling rate for audio playback selected by software embedded class ab power amplifer for ear phone speaker driving (32?)2 embedded high performance 16-bit stereo audio sigma-delta dac pass microsoft ? dtm (whql) usb audio device audio playback digital volume control 6 endpoints supported including endpoint 0 support 1 control, 2 interrupts, 1 isochronous and 2 bulk transfers one hardware implemented isochronous transfer total fifo size are 528 bytes (8, 8, 384, 32, 32, 64 for ep0~ep2,ep4~ep6) 819216 program memory 3528 mcu type data memory ram (bank 0, bank 9) 12884 speaker output data or 12-bit adc converted data ram (bank1, bank2, bank3, bank4) usb audio and 12-bit adc stereo data capture dma 12884 mcu type general purpose data ram (bank5, bank6, bank7, bank8) 6-channel 12-bit a/d converter 2-channel pwm function shared with pb2~pb3 dual programmable attenuator for 2-channel external stereo audio input universal asynchronous receiver transmitter (uart) shared with pb0~pb1 spi interface (master and slave mode) shared with pc4~pc7 programmable frequency divider (pfd) function shared with pc0 power-down function and wake-up reduce power consumption up to 21 bidirectional i/o lines dual 16-bit programmable timer/event counters with overfow interrupts watchdog timer 16-level subroutine nesting bit manipulation instruction 16-bit table read instruction 63 powerful instructions. all instructions executed within one or two machine cycles low voltage reset function((3.0v0.3v) 48-pin lqfp package
rev 1.00 8 ???i? 1?? ? 011 rev 1.00 9 ???i? 1?? ? 011 HT82A824R usb audio mcu general description this HT82A824R is an 8-bit high performance risc microcontroller designed for usb speaker related product applications. the HT82A824R combines a 16-bit dac, usb transceiver, sie (serial interface engine), audio class processing unit, fifo, 8-bit mcu into a single chip. the sigma-delta dac in the HT82A824R is operating at the 48khz or 44.1khz sampling rate. the HT82A824R has a digital programmable gain amplifer. the gain range is from -32db to +6db. the external stereo audio input can be the other source of power amplifer by software control. the HT82A824R has a human interface device function that allows a user to control the playback volume at the device side. the HT82A824R also can mute the analog output signal by the operation of hid buttons. block diagram
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rev 1.00 8 ???i? 1?? ? 011 rev 1.00 9 ???i? 1?? ? 011 HT82A824R usb audio mcu pin assignment

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pin description pin name i/o confguration option description p ?0~p ?3 p ??/mclk p ?5/sclk p ?6/lrck p ?7/sd? t ? i/o pu??-high wake-u ? bidi?ectiona? 8-bit in?ut/out?ut ?o? t. each bit can be configu? ed as a wake-up input by a confguration option. software instructions d etermine if the ? in is a cmos out? ut o? schmitt t?igge? in? ut. configu? ation o? tions dete? mine which ? ins on this ?o?t have ?u??-high ?esisto? s. the out? ut st?uctu? e can be eithe? nmos o? cmos ty? es dete? mined via confguration option. p ??~p ?7 a?e sha?ed with i ? s out?ut. pb0/u? rt(tx) pb1/u? rt(rx) pb?/pwm0 pb3/pwm1 pb? i/o pu??-high wake-u ? bidi ? ectiona ? 5-bit in ? ut/out ? ut ? o ? t. softwa ? e inst? uctions dete ? mine if the pin is a cmos output or schmitt trigger input. confguration options dete?mine which ?ins on this ?o?t have ?u??-high ?esisto?s. pins pb0 and pb1 a?e ?in-sha? ed with the u? rt ? ins tx and rx. note that if the u ? rt function is se?ected? the inte?na? ?u?? -high function ?e? ated to these two ?ins wi?? be disab? ed by ha?dwa? e. the u? rt o? i/o function is se?ected by softwa?e o?tion. pins pb? and pb3 a?e ?in-sha? ed with pwm0 and pwm1. if the pwm function is se ?ected? the inte?na? ?u?? -high function ?e? ated to these two ?ins wi?? be disab?ed by ha?dwa?e. pwm o? i/o function is se?ected by softwa?e o?tion. pc0/ bz pc1/tmr0 pc?/tmr1 pc3/ int pc?/sdo pc5/sdi pc6/ scs pc7/sck i/o pu??-high wake-u ? bidi ? ectiona ? 8-bit in ? ut/out ? ut ? o ? t. softwa ? e inst? uctions dete ? mine if the pin is a cmos output or schmitt trigger input. confguration options dete?mine which ?ins on this ?o?t have ?u??-high ?esisto? s. pin pc0 is sha? ed with the buzze? ?in bz . pins pc1 and pc ? a?e sha? ed with time? in?ut ? ins tmr0 and tmr1. pc3 is sha?ed with exte?na? inte??u?t in?ut int . pins pc? and pc5 a?e sha? ed with se?ia? inte?face ? ins sdo and sdi. pin pc6 is sha ? ed with the se?ia? inte? face s? ave se?ect ? in. pin pc7 is sha?ed with the se?ia? inte?face c?ock signa?. vref_r o C positive vo?tage ?efe?ence fo? d?c conve?te? ?ight channe?. ca?acito?s shou?d be connected to g?ound to kee? f?om the distu?bing signa?. vref_l o C positive vo ? tage ? efe? ence fo? d?c conve? te? ? eft channe? . ca? acito? s shou?d be connected to g?ound to kee? f?om the distu?bing signa?.
rev 1.00 10 ???i? 1?? ? 011 rev 1.00 11 ???i? 1?? ? 011 HT82A824R usb audio mcu pin name i/o confguration option description music_in_r i C powe ? am ?? ifie? in? ut signa? sou? ce if ? egiste ? bit selw =1. the ana? og signa? in? ut wi?? go th?ough the ??og?ammab? e attenuato? and be amplifed by the power amp then output to rout. music_in_l i C powe ? am ?? ifie? in? ut signa? sou? ce if ? egiste ? bit selw =1. the ana? og signa? in? ut wi?? go th?ough the ??og?ammab? e attenuato? and be amplifed by the power amp then output to lout. bi?s C C ca? acito? s shou ? d be connected to g? ound to inc ? ease common mode vo?tage stabi?ity lout o C left d?ive? ana?og out?ut rout o C right d?ive? ana?og out?ut ?n0~?n5 i C 1?-bit ?dc ana?og in?uts osci osco i o C osci? osco a? e connected to an exte?na? 6mhz o? 1? mhz c?ysta?/ ? esonato ?? dete ? mined by softwa?e inst ? uctions? fo ? the inte?na? system c?ock reset i C schmitt t?igge? ?eset in?ut. ?ctive ? ow. usbdn i/o C usbd- ?ine usbdp i/o C usbd+ ?ine v33o o C 3.3v ?egu?ato? out?ut ? vdd1 C C ?udio d?c ?ositive ?owe? su???y ? vss1 C C ?udio d?c negative ?owe? su???y ? g?ound ? vdd? C C audio power amplifer positive power supply ? vss? C C audio power amplifer negative power supply, ground ? vdd3 C C 1?-bit ?dc ?ositive ?owe? su???y ? vss3 C C 1?-bit ?dc negative ?owe? su???y ? g?ound dvdd1 C C positive digita? ?owe? su???y dvss1 C C negative digita? ?owe? su???y ? g?ound absolute maximum ratings supply voltage ................................................................................................ v ss ss input voltage .................................................................................................. v ss 6uhhshuuh .................................................................................................. c to 125c 2shuhshuuh ................................................................................................ c to 85 c 1hkhvhuhvuhvvuvo6uhvvhvhfhhkhuhvshfihhuevoh0 5vfvhvevohkhhyfhfoshuikvhyfhkhu fvehkvhovhkhvshffvsohsuohhsvuhhuhh conditions may affect device reliability.
rev 1.00 10 ???i? 1?? ? 011 rev 1.00 11 ???i? 1?? ? 011 HT82A824R usb audio mcu d.c. characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd o?e? ating vo?tage 5v ?.0 5.0 5.5 v i dd1 o?e?ating cu??ent 5v no ?oad? f sys =1?mhz d?c/p ? o?e?ating C 60 80 m? i dd? o?e?ating cu??ent 5v no ?oad? f sys =1?mhz d?c/p ? off C 6 10 m? i sus sus?end cu??ent 5v no ?oad? system h? lt ? usb t?ansceive? and 3.3v ?egu?ato? on C 300 C u? v il1 in? ut low vo?tage fo? i/o po?ts 5v C 0 C 0.3v dd v v ih1 in? ut high vo?tage fo? i/o po?ts 5v C 0.7v dd C v dd v v il? in? ut low vo?tage ( reset ) 5v C 0 C 0.?v dd v v ih? in? ut high vo?tage ( reset ) 5v C 0.9v dd C v dd v i ol i/o po?t sink cu??ent 5v v ol =0.1v dd C 5 C m? i oh i/o po?t sou?ce cu??ent 5v v oh =0.9v dd C -? C m? r ph pu??-high resistance 5v C 30 ?0 80 k ? v lvr0 low vo ?tage reset 5v C ?.7 3.0 3.3 v v v33o 3.3v regu?ato? out?ut 5v i v33o =-70m? 3.0 3.3 3.6 v d?c+powe? ?m?: test condition: measu ?ement bandwidth ?0hz to ?0khz? f s = 48khz. line output series capacitor with 220f. thd+n thd+n note1 5v 10k ? load C -77 C db snr d? signa? to noise ratio note1 5v 10k ? load C 88 C db dr dynamic range 5v 10k ? load C 90 C db p out out?ut powe? 5v 3? ? load ? thd=0.1% C ?0 C mw/ch 12-bit adc dnl ? dc diffe?entia? non-linea?ity 5v v ref = ?v dd3 =v dd ? t ?d =0.5s C ? C lsb inl ?dc integ?a? non-linea?ity 5v v ref = ?v dd3 =v dd ? t ?d =0.5s C ? C lsb note 1: sine wave input@ 1khz, C6db
rev 1.00 1? ???i? 1?? ? 011 rev 1.00 13 ???i? 1?? ? 011 HT82A824R usb audio mcu a.c. characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 exte?na? c?ysta? 3.3v C C 1? C mhz f sys? system c?ock 3.3v C 6 C 16 mhz t wdtosc watchdog osci ??ato? pe?iod 5v C C 100 C s t res reset in ?ut pu?se width C C 1 C C s t sst system sta?t-u? time? pe?iod C C C 10?? C t sys t int inte??u?t pu?se width C C 1 C C s note: t sys =1/f sys system architecturex a key factor in the high-performance features of the holtek range of microcontrollers is attributed to the internal system architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all operations of the instruction set. it carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o control system with maximum reliability and fexibility . clocking and pipelining the main system clock, derived from a crystal oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to frst obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
rev 1.00 1? ???i? 1?? ? 011 rev 1.00 13 ???i? 1?? ? 011 HT82A824R usb audio mcu
? ? ? ? ? system clocking and pipelining
? ? ? ? ? ? ? ? ? ? instruction fetching program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call, that demand a jump to a non- consecutive program memory address. note that the program counter width varies with the program memory capacity depending upon which device is selected. however, it must be noted that only the lower 8 bits, known as the program counter low register , are directly addressable by user. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writable register. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. the lower byte of the program counter is fully accessible under program control. manipulating the pcl might cause program branching, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section.
rev 1.00 1? ???i? 1?? ? 011 rev 1.00 15 ???i? 1?? ? 011 HT82A824R usb audio mcu mode program counter bits b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 initia? reset 0 0 0 0 0 0 0 0 0 0 0 0 0 usb inte??u?t 0 0 0 0 0 0 0 0 0 0 1 0 0 time ?/event counter 0 overfow 0 0 0 0 0 0 0 0 0 1 0 0 0 time ?/event counter 1 overfow 0 0 0 0 0 0 0 0 0 1 1 0 0 p?ay inte??u?t 0 0 0 0 0 0 0 0 1 0 0 0 0 mu?ti function inte??u?t 0 0 0 0 0 0 0 0 1 0 1 0 0 rese?ved 0 0 0 0 0 0 0 0 1 1 0 0 0 ski? p?og?am counte?+? loading pcl pc1? pc11 pc10 pc9 pc8 @7 @6 @5 @? @3 @? @1 @0 jum?? ca?? b?anch #1? #11 #10 #9 #8 #7 #6 #5 #? #3 #? #1 #0 retu?n f?om sub?outine s1? s11 s10 s9 s8 s7 s6 s5 s? s3 s? s1 s0 note: pc12~pc8: current program counter bits @7~@0: pcl bits #12~#0: instruction code address bits s12~s0: stack register bits stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has 16 levels and is neither part of the data nor part of the program space, and can neither be read from nor written to. the activated level is indexed by the stack pointer, sp, which can also neither be read from nor written to. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overfow. precautions should be taken to avoid such cases, which might cause unpredictable program branching.

rev 1.00 1? ???i? 1?? ? 011 rev 1.00 15 ???i? 1?? ? 011 HT82A824R usb audio mcu arithmetic and logic unit C alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: arithmetic operations add, addm, adc, adcm,sub, subm, sbc, sbcm, daa logic operations and, or, xor, andm, orm,xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca,rlc increment and decrement inca, inc, deca, dec branch decision jmp, sz, sza, snz, siz, sdz, siza,sdza, call, ret, reti program memory the program memory is the location where the user code or program is stored. the device contains one-time programmable, otp, memory where users can program their application code into the device. by using the appropriate programming tools, otp devices offer users the fexibility to freely develop their applications, which may be useful during debug or for products requiring frequent upgrades or program changes. otp devices are also applicable for use in applications that require low or medium volume production runs. organisation the program memory has a capacity of 8k by 16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by separate table pointer registers. special vectors within the program memory, certain locations are reserved for special usage such as reset and interrupts. location 000h this vector is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. location 004h this vector is used by the usb interrupt. if a usb interrupt occurs, the program will jump to this location and begin execution if the usb interrupt is enabled and the stack is not full. location 008h this vector is used by the timer/event counter 0. if a counter overfow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full. location 00ch this vector is used by the timer/event counter 1. if a counter overfow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full.
rev 1.00 16 ???i? 1?? ? 011 rev 1.00 17 ???i? 1?? ? 011 HT82A824R usb audio mcu location 010h this vector is used by the play interrupt service program. if play data occurs, the program will jump to this location and begin execution if the play interrupt is enabled and the stack is not full. location 014h this vector is used by the multi-function interrupt. if an interrupt results from a serial interface interrupt, an end of 12-bit a/d conversion cycle, an external interrupt or an uart bus interrupt, the program will jump to this location and begin execution if the relevant interrupt is enabled and the stack is not full.
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rev 1.00 16 ???i? 1?? ? 011 rev 1.00 17 ???i? 1?? ? 011 HT82A824R usb audio mcu look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. to use the look-up table, the table pointers must frst be setup which point to the data in the program memory which is to be read. in this device there are two table pointers, the low byte pointer, tblp and the high byte pointer, tbhp. however, the high byte pointer, tbhp, can only be used if it is enabled using confguration options. using both table pointers enables any area in the program memory to be addressed while if only the low byte pointer, tblp, is used then only the present page or last page can be addressed. if the confguration options do not enable the high byte pointer, then after setting up the low table pointer, tblp, the table data can be retrieved from the current program memory page or last program memory page using the tabrdc [m] or tabrdl [m] instructions, respectively. when these instructions are executed, the lower order table byte from the program memory will be transferred to the user defned data memory register [m] as specifed in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. the following diagram illustrates the addressing/data fow of the look-up table using the single table address pointer tblp:
single address pointer look-up table if the configuration options enable the high table pointer, tbhp, then this register together with the low table pointer, tblp, can be used together as a pair to point to any located in the program memory. after setting up both the low and high byte table pointers, the table data can then be retrieved from any area of program memory using the tabrdc [m] instruction or from the last page of the program memory using the tabrdl [m] instruction. when either of these instructions are executed, the lower order table byte from the program memory will be transferred to the user defned data memory register [m] as specifed in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. the following diagram illustrates the addressing/data fow of the look-up table using the dual table address pointers tblp and tbhp:
dual address pointer look-up table
rev 1.00 18 ???i? 1?? ? 011 rev 1.00 19 ???i? 1?? ? 011 HT82A824R usb audio mcu table program example the following example shows how the table pointer and table data is defned and retrieved from the micro controller using the single table data pointer, tblp. this example uses raw table data located in the last page which is stored there using the org statement. the value at this org statement is 1f00h which refers to the start address of the last page within the 8k program memory of device. the table pointer is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address 1f06h or 6locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the tabrdc [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrdl [m] instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use the table read instructions. if using the table read instructions, the interrupt service routines may change the value of tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise table pointer - note that this address ; is referenced mov tblp,a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempregl ; data at prog. memory address 1f06h transferred to ; tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 ; data at prog. memory address 1f05h transferred to ; tempreg2 and tblh ; in this example the data 1ah is transferred to ; tempreg1 and data 0fh to register tempreg2 ; the value 00h will be transferred to the high byte ; register tblh : : org 1f00h ; sets initial address of last page dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh table location instruction table location b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 t ?brdc [m] pc1? pc11 pc10 pc9 pc8 @7 @6 @5 @? @3 @? @1 @0 t ? brdl [m] 1 1 1 1 1 @7 @6 @5 @? @3 @? @1 @0 note: pc12~pc8: current program counter bits tbhp register bit4~bit0 when tbhp option is enabled @7~@0: table pointer tblp bits
rev 1.00 18 ???i? 1?? ? 011 rev 1.00 19 ???i? 1?? ? 011 HT82A824R usb audio mcu data memory the data memory is divided into three functional groups: namely; special purpose data memory, read only data memory and general data memory. bank0: 1608 bits, bank1~bank4: 12884 bits (read only), bank5~bank8: 12884 bits, bank9: 1928 bits. most are read/write, but some are read only. the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. the special purpose data memory is an area of ram where special function registers are located. these registers have fixed locations and are necessary for correct operation of the device. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. the general purpose data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. the read only data memory is used for audio output data or dac converted data memory area, and its read only. organisation the data ram memory is subdivided into several banks, known as bank 0 to bank 9, all of which are implemented in 8-bit wide ram. the bank 0 data memory is subdivided into two sections, the special purpose data memory and the general purpose data memory. the start address of the bank 0 data memory is the address 00h and the last data memory address is ffh. the bank 1~4 data memory consist only of read only data memory which are reserved for usb speaker output data or adc (an0~an1) converted data. the data memory arrangement for usb speaker output data or adc converted data is determined by software option. the bank 5~9 data memory consist only of general purpose data memory. the start address of the data memory is the address 40h for bank 1~9 and the last data memory address is bfh for bank 1~8 and ffh for bank 9. selection of which bank is to be used is implemented using the bank pointer .

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? data memory structure note: most of the ram data memory bits can be directly manipulated using the set [m].i and clr [m].i instructions with the exception of a few dedicated bits. the ram data memory can also be accessed through the memory pointer registers mp0 and mp1.
rev 1.00 ?0 ???i? 1?? ? 011 rev 1.00 ?1 ???i? 1?? ? 011 HT82A824R usb audio mcu general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user program for both read and write operations. by using the set [m].i and clr [m].i instructions individual bits can be set or reset under program control giving the user a large range of fexibility for bit manipulation in the data memory. as the general purpose data memory exists in several banks, bank 0 to bank 9, it is necessary to frst ensure that the bank pointer is properly set to the correct value before accessing the general purpose data memory. for example, when the bank pointer is set to the value 00h, data from bank 0 will be accessed and when set to the value 01h, data from bank 1 will be accessed. note that bank1~9 must be accessed indirectly using the memory pointer mp1 and the indirect addressing register iar1. special purpose data memory this area of data memory, is located in bank 0, where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers can be read from and written to but some are protected and are read only, the details of which are located under the relevant special function register section. note that for locations that are unused, any read instruction to these addresses will return the value 00h.the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4.

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rev 1.00 ?0 ???i? 1?? ? 011 rev 1.00 ?1 ???i? 1?? ? 011 HT82A824R usb audio mcu special function registers to ensure successful operation of the microcontroller, certain internal registers are implemented in the data memory area. these registers ensure correct operation of internal functions such as timers, interrupts, usb port, etc., as well as external functions such as i/o data control. the location of these registers within the data memory begins at the address 00h. any unused data memory locations between these special function registers and the point where the general purpose memory begins is reserved and attempting to read data from these locations will return a value of 00h. indirect addressing register C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specifed by their corresponding memory pointer, mp0 or mp1. acting as a pair, iar0 and mp0 can together only access data from bank 0, while the iar1 and mp1 register pair can access data from bank 0 to bank 9. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointer C mp0, mp1 for all devices, two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specifed by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0 only, while mp1 and iar1 are used to access data from bank 0 to bank 9. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 db adres2 db adres3 db adres4 db block db code .section at 0 code org 00h start: mov a,04h setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with frst ram address setup memory pointer with frst ram address clr iar0 ; clear the data at address defned by mp0 the important point to note here is that in the example shown a bove, no reference is made to specifc data memory addresses.
rev 1.00 ?? ???i? 1?? ? 011 rev 1.00 ?3 ???i? 1?? ? 011 HT82A824R usb audio mcu bank pointer C bp the data memory is divided into several banks, known as bank 0 to bank 9. selecting the required data memory area is achieved using the bank pointer. if data in bank 0 is to be accessed, then the bp register must be loaded with the value 00, while if data in bank 1 is to be accessed, then the bp register must be loaded with the value 01. using memory pointer mp0 and indirect addressing register iar0 will always access data from bank 0, irrespective of the value of the bank pointer. the data memory is initialised to bank 0 after a reset, except for the wdt time-out reset in the power down mode, in which case, the data memory bank remains unaffected. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer.
accumulator C acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted.
rev 1.00 ?? ???i? 1?? ? 011 rev 1.00 ?3 ???i? 1?? ? 011 HT82A824R usb audio mcu look-up table registers C tblp, tblh, tbhp these three special function registers are used to control operation of the look-up table, which is stored in the program memory. tblp is the table low byte pointer and indicates the lowest 8-bit address location where the table data is located. tbhp is the table high byte pointer and indicates the highest bit address location where the table data is located. the tbhp high byte table pointer can only be used if its confguration option is selected. the table pointers must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. if the tbhp confguration is enabled, then the tblp and tbhp register pair can be used together with the tabrdc instruction to point directly to any location in the program memory. tblh is the location where the higher order byte of the table data is stored after a table read data instruction has been executed. the lower order table data byte is transferred to a user defned location. watchdog timer register C wdts the watchdog feature of the microcontroller provides an automatic reset function giving the microcontroller a means of protection against spurious jumps to incorrect program memory addresses. to implement this, a timer is provided within the microcontroller which will issue a reset command when its value overfows. to provide variable watchdog timer reset times, the watchdog timer clock source can be divided by various division ratios, the value of which is set using the wdts register. by writing directly to this register, the appropriate division ratio for the watchdog timer clock source can be setup. note that only the lower 3 bits are used to set division ratios between 1 and 128. status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (to). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller . with the exception of the to and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf fag. in addition, operations related to the status register may give different results due to the different instruction operations. the to fag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt instruction. the pdf fag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ov is set if an operation results in a carry into the highest- order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out.
rev 1.00 ?? ???i? 1?? ? 011 rev 1.00 ?5 ???i? 1?? ? 011 HT82A824R usb audio mcu in addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.

? ? ? ?? ? ?- ?? status register interrupt control registers C intc0, intc1, mfi1c these three 8-bit registers, known as the intc0, intc1 and mfi1c control the operation of the interrupts. by setting various bits within this register using standard bit manipulation instructions, the enable/disable function of the all interrupts can be independently controlled. a master interrupt bit within this register, the emi bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. this bit is cleared when an interrupt routine is entered to disable further interrupt and is set by executing the reti instruction. note in situations where other interrupts may require servicing within present interrupt service routines, the emi bit can be manually set by the program after the present interrupt service routine has been entered. timer/event counter registers C tmrl/tmrh, tmrc the device contains two 16-bit timer/event counters. each timer/event counter has an associated register pair, known as tmr0l/tmr0h and tmr1l/tmr1h which are the locations where the timers 16-bit value is located. each timer also has an associated control register, known as tmr0c and tmr1c which contains the setup information for the associated timer. input/output ports and control registers within the area of special function registers, the i/o registers and their associated control registers play a prominent role. all i/o ports have a designated register correspondingly labeled as pa, pb and pc. these labeled i/o registers are mapped to specifc addresses within the data memory as shown in the data memory table, which are used to transfer the appropriate output or input data on that port. with each i/o port there is an associated control register labeled pac, pbc and pcc, also mapped to specifc addresses with the data memory. the control register specifes which pins of that port are set as inputs and which are set as outputs. to setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. during program initialization, it is important to frst setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the i/o ports. one fexible feature of these registers is the ability to directly program single bits using the set [m].i and clr [m]. i instructions. the ability to change i/o pins from output to input and vice versa by manipulating specifc bits of the i/o control registers during normal program operation is a useful feature of these devices.
rev 1.00 ?? ???i? 1?? ? 011 rev 1.00 ?5 ???i? 1?? ? 011 HT82A824R usb audio mcu port a wake-up control register C pa_wake_ctrl this register is used to select the edge type that triggers the wake-up function on the port a pins. if the confguration options select some or all of the port a pins to have a wake-up function then this register can be used to select either whether the active edge is a negative or positive transition. only port a is allowed this selection. pulse width modulator registers C pwm0, pwm1, pwmc the device 2 integrated pulse width modulators. each one has its own independent register, known as pwm0 and pwm1. the 8-bit contents of each of these registers defne the duty cycle value for the modulation cycle of the corresponding pulse width modulator. the pwmc is the control register for the pwm functions and controls the mode selection and on/off function. a/d converter registers C adrl, adrh, adcr, acsr the device contains a single 6-channel 12-bit a/d converter. the correct operation of the a/d requires the use of two data registers, a control register and a clock source register. there are two data registers, a high byte data register known as adrh, and a low byte data register known as adrl. these are the register locations where the digital value is placed after the completion of an analog to digital conversion cycle. the channel selection and confguration of the a/d converter is setup via the control register adcr while the a/d clock frequency is defned by the clock source register, acsr. usb registers the device contains an internal usb port which is controlled via several registers. these are used to setup the usb operation, the external pins, error handling etc. as this register list is too numerous to list here details can be found in the relevant usb description. pfd registers C pfdc, pfdd the device contains a fully integrated programmable frequency driver otherwise known as the pfd. two registers control the overall operation of the pfd to determine the output frequency and the function enable/disable. other registers the device contains several other special function registers for control of various internal functions. as their functional description is too detailed to be described here their details will be provided in the relevant functional description section.
rev 1.00 ?6 ???i? 1?? ? 011 rev 1.00 ?7 ???i? 1?? ? 011 HT82A824R usb audio mcu input/output ports holtek microcontrollers offer considerable fexibility on their i/o ports. with the input or output designation of every pin fully under user program control, pull-high options for all ports and wake- up options on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the microcontroller provides a maximum of 21 bidirectional input/output lines labeled with port names pa, pb and pc. these i/o ports are mapped to the data memory with addresses as shown in the special purpose data memory table. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a,[m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selectable via confguration options and are implemented using a weak pmos transistor. port wake-up if the halt instruction is executed, the device will enter the power down mode, where the system clock will stop resulting in power being conserved, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is a logical transition on one of the port a~port c pins from high to low. after a halt instruction forces the microcontroller into entering the power down mode, the device will remain idle or in a low- power state until the logic condition of the selected wake-up pin on port a~port c changes from high to low. this function is especially suitable for applications that can be woken up via external switches. note that each pin on port a~port c can be selected individually using configuration options to have this wake-up feature. additionally port a pins have an additional selection allowing their wake-up function to be either negative or positive edge triggered. this option is provided using the pa_wake_ctrl register. only port a pins have this feature, the wake-up pins on the other ports are only negative edge triggered.

port a wake-up
rev 1.00 ?6 ???i? 1?? ? 011 rev 1.00 ?7 ???i? 1?? ? 011 HT82A824R usb audio mcu i/o port control registers each i/o port has its own control register pac, pbc and pcc, to control the input/output configuration. with this control register, each cmos output or input with or without pull-high resistor structures can be reconfgured dynamically under software control. each of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pin-shared functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these diffculties can be overcome. for some pins, the chosen function of the multi-function i/o pins is set by software options while for others the function is set by application program control. serial interface the serial interface pins sdo, sdi, scs and sck are pin-shared with the i/o pins pc4, pc5, pc6 and pc7. for applications not requiring serial interface, the pin-shared pins can be used as a normal i/o pin. external interrupt the external interrupt pin int is pin-shared with the i/o pin pc3. for applications not requiring an external interrupt input, the pin-shared external interrupt pin can be used as a normal i/o pin, however to do this, the external interrupt enable bits in the mfi1c register must be disabled. external timer/event counter input the external timer pins tmr0/tmr1 are pin-shared with the i/o pins pc1/pc2. if these shared pins are to be used as a timer/event counter inputs, then the timer/event counter must be confgured to be in the event counter or pulse width measurement mode. this is achieved by setting the appropriate bits in the relevant timer/event counte r control register. the pin must also be setup as an input by setting the appropriate bit in the port control register pull-high resistor options can also be selected via the appropriate port pull-high confguration option. if the shared pin is to be used as a normal i/o pin, then the external timer input function must be disabled, by ensuring that the corresponding timer/event counter is confgured to be in the off mode or timer mode. pfd output the device contains a pfd function whose single output is pin-shared with pc0. the output function of this pin is chosen via software. note that the corresponding bit of the port control register, pcc.0, must setup the pin as an output to enable the pfd output. if the pcc port control register has setup the pin as an input, then the pin will function as a normal logic input with the usual pull-high option, even if the pfd confguration option has been selected.
rev 1.00 ?8 ???i? 1?? ? 011 rev 1.00 ?9 ???i? 1?? ? 011 HT82A824R usb audio mcu spi interface the device contains an internal spi interface whose pins are shared with i/o pins pc4~pc7. the spi interface control register, sbcr, is used to determine if these pins are to be used as normal i/ o pins or as spi interface pins. uart the uart pins tx/rx are pin-shared with the i/o pins pb0/pb1. for applications not requiring an uart, the pin-shared uart pins can be used as a normal i/o pins, however, to do this, the uart interrupt enable bits in the mfi1c register must be disabled. pwm the pwm pins pwm0/pwm1 are pin-shared with the i/o pins pb2/pb3. for applications not requiring pwm, the pin-shared pwm pins can be used as a normal i/o pins. i/o pin structures the following diagrams illustrate the i/o pin internal structures. as the exact logical construction of the i/o pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins.

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rev 1.00 ?8 ???i? 1?? ? 011 rev 1.00 ?9 ???i? 1?? ? 011 HT82A824R usb audio mcu programming considerations within the user program, one of the frst things to consider is port initialisation. after a reset, all of the data and port control register will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. if the pac, pbc and pcc port control registers, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated pa, pb and pc port data registers are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct value into the port control register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports.
read/write timing timer/event counters the provision of timers form an important part of any microcontroller giving the designer a means of carrying out time related functions. the device contains two internal 16-bit count-up timers each of which has three operating modes. the timer can be configured to operate as a general timer, external event counter or as a pulse width measurement device. there are three registers related to each of the timer/event counters, these are a pair or timer registers and a control register. the register pairs tmr0l/tmr0h and tmr1l/tmr1h contain the 16-bit timing value. writing to these register pairs places an initial starting value in the timer/event counter preload registers while reading them retrieves the contents of the timer/event counter. the tmr0c and tmr1c registers are the timer/event counter control registers, which defne the timer options, and determines how the timers are to be used. the timer clock source can be confgured to come from the internal system clock source or from an external clock on shared pin pc1/tmr0 and pc2/tmr1. timer/event counter 0 structure
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rev 1.00 30 ???i? 1?? ? 011 rev 1.00 31 ???i? 1?? ? 011 HT82A824R usb audio mcu

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rev 1.00 30 ???i? 1?? ? 011 rev 1.00 31 ???i? 1?? ? 011 HT82A824R usb audio mcu timer control register C tmr0c, tmr1c the fexible features of the holtek microcontroller timer/event counters enable them to operate in three different modes, the options of which are determined by the contents of their control register, which has the name tmr0c and tmr1c. it is the timer control register together with their corresponding timer register pair that control the full operation of the timer/event counter. before the timer/event counter can be used, it is essential that the timer control register pair is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. to choose which of the three modes the timer/event counter is to operate in, either in the timer mode, the event counting mode or the pulse width measurement mode, bits 7 and 6 of the timer control register, which are known as the bit pair tm1/tm0, must be set to the required logic levels. the timer/event counter on/off bit, which is bit 4 of the timer control register and known as ton, provides the basic on/off control of the timer/event counter. setting the bit high allows the timer/event counter to run, clearing the bit stops it running. if the timer/ event counter is in the event count or pulse width measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the timer control register which is known as te.
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? ? ? ? ? ? ? ? ? timer/event counter 0/1 control register confguring the timer mode in this mode, the timer can be utilised to measure fxed time intervals, providing an internal interrupt signal each time the counter overfows. to operate in this mode, bits tm1 and tm0 of the tmrc register must be set to 1 and 0 respectively. in this mode, the internal clock is used as the timer clock. the input clock frequency to the timer is f sys /4. the timer-on bit, ton, must be set high to enable the timer to run. each time an internal clock high to low transition occurs, the timer increments by one. when the timer is full and overfows, the timer will be reset to the value already loaded into the preload register and continue counting. if the timer interrupt is enabled, an interrupt signal will also be generated. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the interrupt control register, intc0, is reset to zero.
timer mode timing chart
rev 1.00 3? ???i? 1?? ? 011 rev 1.00 33 ???i? 1?? ? 011 HT82A824R usb audio mcu confguring the event counter mode in this mode, a number of externally changing logic events, occurring on the external timer pin, can be recorded by the timer/event counter. to operate in this mode, the operating mode select bit pair in the timer control register must be set to the correct value. in this mode the external timer pin is used as the timer/event counter clock source. after the other bits in the timer control register have been setup, the enable bit, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run. if the active edge select bit, which is bit 3 of the timer control register, is low, the timer/event counter will increment each time the external timer pin receives a low to high transition. if the active edge select bit is high, the counter will increment each time the external timer pin receives a high to low transition. when it is full and overfows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/ event counter interrupt enable bit in the interrupt control register , intc0, is reset to zero. as the external timer pin is shared with an i/o pin, to ensure that the pin is confgured to operate as an event counter input pin, two things have to happen. the frst is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the event counting mode, the second is to ensure that the port control register confgures the pin as an input. it should be noted that in the event counting mode, even if the microcontroller is in the power down mode, the timer/event counter will continue to record externally changing logic events on the timer input pin. as a result when the timer overfows it will generate a timer interrupt and corresponding wake- up source.
event counter mode timing chart confguring the pulse width measurement mode in this mode, the timer/event counter can be utilised to measure the width of external pulses applied to the external timer pin. to operate in this mode, the operating mode select bit pair in the timer control register must be set to the correct value. in this mode the internal clock, f sys /4, is used as the timer/event counter clock. after the other bits in the timer control register have been setup, the enable bit, which is bit 4 of the timer control register, can be set high to enable the timer/event counter, however it will not actually start counting until an active edge is received on the external timer pin. if the active edge select bit, which is bit 3 of the timer control register, is low, once a high to low transition has been received on the external timer pin, the timer/event counter will start counting until the external timer pin returns to its original high level. at this point the enable bit will be automatically reset to zero and the timer/event counter will stop counting. if the active edge select bit is high, the timer/event counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin returns to its original low level. as before, the enable bit will be automatically reset to zero and the timer/ event counter will stop counting. it is important to note that in the pulse width measurement mode, the enable bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control. the residual value in the timer/event counter, which can now be read by the program, therefore represents the length of the pulse received on the external timer pin. as the enable bit has now been reset, any further transitions on the external timer pin will be ignored.
rev 1.00 3? ???i? 1?? ? 011 rev 1.00 33 ???i? 1?? ? 011 HT82A824R usb audio mcu not until the enable bit is again set high by the program can the timer begin further pulse width measurements. in this way, single shot pulse measurements can be easily made. it should be noted that in this mode the timer/event counter is controlled by logical transitions on the external timer pin and not by the logic level. when the timer/event counter is full and overfows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the interrupt control register, intc0, is reset to zero. as the external timer pin is shared with an i/o pin, to ensure that the pin is confgured to operate as a pulse width measurement pin, two things have to happen. the frst is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the pulse width measurement mode, the second is to ensure that the port control register confgures the pin as an input.
? ? ? ? ? ? ? ? - ?- ? ? pulse width measure mode timing chart i/o interfacing the timer/event counter, when confgured to run in the event counter or pulse width measurement mode, requires the use of an external pin for correct operation. as the external timer pin is pin- shared with an i/o pin, it must be configured correctly to ensure it is setup for use as a timer/ event counter input and not as a normal i/o pin. this is implemented by ensuring that the mode select bits in the timer/event counter control register, select either the event counter or pulse width measurement mode. additionally the port control register bit for this pin must be set high to ensure that the pin is setup as an input. any pull high confguration for this pins will remain valid even if the pin is used as a timer/event counter input.
rev 1.00 3? ???i? 1?? ? 011 rev 1.00 35 ???i? 1?? ? 011 HT82A824R usb audio mcu programming considerations when configured to run in the timer mode, the f sys /4 is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. in this mode, when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. for the pulse width measurement mode, the f sys /4 clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. as this is an external event and not synchronized with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. as a result there may be small differences in measured values requiring programmers to take this into account during programming. the same applies if the timer is confgured to be in the event counting mode which again is an external event and not synchronised with the f sys /4 clock. when the timer/event counter is read or if data is written to the preload registers, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. care must be taken to ensure that the timers are properly initialised before using them for the frst time. the associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. the edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly confgured for the required application. it is also important to ensure that an initial value is frst loaded into the timer register before the timer is switched on; this is because after power-on the initial value of the timer register is unknown. after the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control register. note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. setting the timer enable bit high together with a mode bit modifcation, may lead to improper timer operation if executed as a single timer control register byte write instruction. when the timer/event counter overfows, its corresponding interrupt request fag in the interrupt control register will be set. if the timer interrupt is enabled this will in turn generate an interrupt signal. however irrespective of whether the timer interrupt is enabled or not, a timer/event counter overfow will also generate a wake-up signal if the device is in a power-down condition. this situation may occur if the timer/ event counter is in the event counting mode and if the external signal continues to change state. in such a case, the timer/event counter will continue to count these external events and if an overfow occurs the device will be woken up from its power-down condition. to prevent such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the halt instruction to enter the power down mode.
rev 1.00 3? ???i? 1?? ? 011 rev 1.00 35 ???i? 1?? ? 011 HT82A824R usb audio mcu timer program example this program example shows how the timer/event counter registers are setup, along with how the interrupts are enabled and managed. note how the timer/event counter is turned on, by setting bit 4 of the timer control register. the timer/event counter can be turned off in a similar way by clearing the same bit. this example program sets the timer/event counter to be in the timer mode, which uses the internal system clock as the clock source. org 04h ; usb interrupt vector jmp usbint reti org 08h ; timer/event counter 0 interrupt vector jmp tmr0int ; jump here when timer0 overfows : org 20h ; main program ;internal timer/event counter 0 interrupt routine tmr0int: : ; timer/event counter 0 main program placed here : reti : : begin: ;setup timer0 registers mov a,09bh ; setup preload value C timer0 counts from this value to ffffh mov tmr0l,a ; mov a,00h mov tmr0h,a ; mov a,080h ; setup timer0 control register mov tmr0c,a ; timer mode ; setup interrupt register mov a,005h ; enable master interrupt and timer interrupt mov intc0,a set tmr0c.4 ; start timer0 - note mode bits must be previously setup programmable frequency divider C pfd the programmable frequency divider function, pfd, allows the generation of a user defined frequency. the clock source for the pfd is the system clock divided by 4, which after being divided by 16 is then passed through a programmable prescaler and the pfdd register allows a range of user defned frequencies to be generated. overall operation of the pfd is controlled using two registers, the pfdc register and the pfdd register. as the pfd output pin is pin-shared with i/o pin pc0, the pfd_io bit in the pfdc register is used to select whether the pin is to be used an a normal i/o function or to be used as a pfd output. the pfden bit is used to control the overall on/off function of the pfd, while bits pres0 and pres1 are used to select the frequency division ratio of the prescaler. the pfdd register provided further division of the clock source, however this register can only be written to when the pfd function is enabled. if the pfd function is disabled, then all write operations to the pfdd register will be inhibited. when the pfd is disabled note that the pfdd register will be automatically cleared. the pfdd contents, the pfd must be enabled. when the generator is disabled, the pfdd is cleared by hardware. the bz signal comes from an internal pfd generator output.
rev 1.00 36 ???i? 1?? ? 011 rev 1.00 37 ???i? 1?? ? 011 HT82A824R usb audio mcu

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rev 1.00 36 ???i? 1?? ? 011 rev 1.00 37 ???i? 1?? ? 011 HT82A824R usb audio mcu power amplifer the selw bit in the pfdc register is used to control the power amplifier input source. the application program should set selw =1 when the power amplifer signal source is from music_ in_l and music_in_r, otherwise the speaker will output usb audio data. lout rout powe? ?m? m u x music_in_l 16-bit d/? out?ut selw=0 selw=1 p?og?ammab?e ?ttenuato? (l) music_in_r p?og?ammab?e ?ttenuato? (r) programmable attenuator the device includes two fully integrated programmable attenuators for two external audio input pins, music_in_l and music_in_r. the attenuators are used to reduce the amplitude and power of the external audio input signal before entering the power amplifer. the attenuators are fully under the control of two internal registers, attenu_ctrl_l and attenu_ctrl_r, one for each attenuator. these registers control the programmable gain function and mute function. the range of programmable gain is from 0 db to a minimum of -22.5 db, controlled by attenu_ctrl_l[0:6] and attenu_ctrl_r[0:6] bits . the resolution of the attenuator is 0.5 db per step. the programmable attenuator mute function is controlled by the attenu_muteb_l(r) bit. if this bit is cleared to 0, that will enable the mute function and the power amp output voltage will be forced to a level of half the power supply. atten_ctrl_l and atten_ctrl_r registers
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rev 1.00 38 ???i? 1?? ? 011 rev 1.00 39 ???i? 1?? ? 011 HT82A824R usb audio mcu interrupts interrupts are an important part of any microcontroller system. when a usb interrupt, play data valid interrupt, a timer/event counter overfow, reception of spi data , external interrupt, uart bus interrupt or a/d interrupt is occurs, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device provides a usb interrupt, two internal timer/event counter interrupts, a play data valid interrupt and a multi function interrupt. this latter multi-function interrupt represents the serial interface interrupt, an external interrupt, an uart bus interrupt or a/d interrupt. interrupt registers overall interrupt control, which means interrupt enabling and request fag setting, is controlled by three interrupt control registers intc0, intc1 and mfi1c which are located in the data memory. by controlling the appropriate enable bits in this register each individual interrupt can be enabled or disabled. also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. the global enable fag if cleared to zero will disable all interrupts. interrupt operation a usb interrupt, a play data valid interrupt, a timer/event counter overfow, an spi interrupt, an a/d conversion complete interrupt, an active edge on the external interrupt pin or an uart bus interrupt will all generate an interrupt request by setting their corresponding request fag, if their appropriate interrupt enable bit is set. when this happens, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp statement which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti statement, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request fags, are shown in the following diagram with their order of priority. once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the emi bit will be cleared automatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full.
rev 1.00 38 ???i? 1?? ? 011 rev 1.00 39 ???i? 1?? ? 011 HT82A824R usb audio mcu interrupt priority interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding interrupts are enabled. in case of simultaneous requests, the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source priority vector usb inte??u?t 1 0?h timer/event counter 0 overfow ? 08h timer/event counter 1 overfow 3 0ch p?ay inte??u?t ? 10h mu?ti function 1 inte??u?t sub?outine: se?ia? inte?face inte??u?t? ?/d inte??u?t? exte?na? inte??u?t? u? rt bus inte??u?t C C in cases where both usb and play interrupts are enabled and where an usb and play interrupt occurs simultaneously, the usb interrupt will always have priority and will therefore be serviced first. suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occurrences.

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rev 1.00 ?0 ???i? 1?? ? 011 rev 1.00 ?1 ???i? 1?? ? 011 HT82A824R usb audio mcu usb interrupt the usb interrupt will be triggered by any of the following usb events resulting in the related interrupt request fag, usbf; bit 4 of intc0, being set: a pc access of the corresponding usb fifo a usb suspend signal from the pc a usb resume signal from the pc a usb reset signal when the interrupt is enabled, the stack is not full and the usb interrupt is active, a subroutine call to location 04h will occur. the interrupt request fag, usbf, and emi bits will be cleared to disable other interrupts. when the pc host accesses the HT82A824R fifo, the corresponding usr request bit is set, and a usb interrupt is triggered. in this way the user can determine which fifo has been accessed. when the interrupt has been serviced, the corresponding bit will be automatically cleared. when the HT82A824R receives a usb suspend signal from the host pc, the suspend line, bit0 of the usc register, in the HT82A824R is set and a usb interrupt is also triggered. also when the device receives a resume signal from the host pc, the resume line, bit3 of the usc register, is set and a usb interrupt generated. timer/event counter interrupt for a timer/event counter interrupt to occur, the global interrupt enable bit, emi, and the corresponding timer interrupt enable bit, et0i or et1i, must first be set. an actual timer/event counter interrupt will take place when the timer/event counter request fag, t0f or t1f, is set, a situation that will occur when the relevant timer/event counter overfows. when the interrupt is enabled, the stack is not full and a timer/event counter 0 overfow occurs, a subroutine call to the timer 0 interrupt vector at location 08h, will take place. if a timer/event counter 1 overfow occurs, a subroutine call to the timer 1 interrupt vector at location 0ch will take place. when the interrupt is serviced, the timer interrupt request fag, t0f or t1f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. play interrupt for a play interrupt to occur, the global interrupt enable bit, emi, and the corresponding play interrupt bit, eplai, must first be set. an actual play interrupt will take place when the play interrupt request flag, playf, is set, a situation that will occur at a regular play frequency of 44.1khz if the play_mode bit in the mode_ctrl register is set high. if this bit is not high, then the play interrupt frequency will be 48khz. when the interrupt is enabled, the stack is not full and a play interrupt occurs, a subroutine call to the play interrupt vector at location 10h, will take place. when the interrupt is serviced, the play interrupt request fag, playf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts.
rev 1.00 ?? ???i? 1?? ? 011 rev 1.00 ?3 ???i? 1?? ? 011 HT82A824R usb audio mcu multi function interrupt an additional interrupt known as the multi-function interrupt is provided. unlike the other interrupts, this interrupt has no independent source, but rather is formed from four other existing interrupt sources, namely the serial interface interrupt, the a/d converter interrupt, the external interrupt and the uart bus interrupt. the multi-function interrupt is enabled by setting the emf1i bit, which is bit 1 of the intc1 register. an actual multi-function interrupt will be initialised when the multi-function interrupt request flag mff1 is set, this is bit 5 of the intc1 register. when the master interrupt global bit is set, the stack is not full and the corresponding emf1i interrupt enable bit is set, a multi-function internal interrupt will be generated when either a serial interface interrupt or an a/d converter interrupt, an external interrupt occurs or an uart bus interrupt. this will create a subroutine call to its corresponding vector location 014h. when a multi-function internal interrupt occurs, the multi-function request fag mff1 will be reset and the emi bit will be cleared to disable other interrupts. however, it must be noted that the request fags from the original source of the multi-function interrupt, namely the serial interface interrupt or the a/d converter, the external interrupt or the uart bus interrupt will not be automatically reset and must be manually reset by the user.

? ? ? ? ? ? ? ? ?? ? ??? ?? ? ? ?? ?? ? mfi1c register
rev 1.00 ?? ???i? 1?? ? 011 rev 1.00 ?3 ???i? 1?? ? 011 HT82A824R usb audio mcu external interrupt the device contains an external interrupt function controlled by the external pin int . for an external interrupt to occur, the pin must be setup as an interrupt input pin by ensuring that the corresponding external interrupt enable bit is frst set. this is bit 2 in the mfi1c register and known as eei. an external interrupt is triggered by a negative edge transition on the external interrupt pin int , after which the related interrupt request fag, eif, which is bit 6 in the mfi1c register, will be set. the interrupt vector for the external interrupt is the multi-function interrupt located at 014h. therefore if the multi-function and external interrupts are enabled, the stack is not full and a negative logical transition occurs on pin int , a subroutine call to location 014h will take place. the multi-function interrupt request fag mff1 will be reset automatically and the emi bit will be cleared to disable other interrupts. the external interrupt fag will not be reset automatically and needs to be reset manually by the application program. the external interrupt pin int is pin-shared with i/o pin pc3 and can only be confgured as external interrupt pins if the interrupt is enabled and if the pin is programmed as an input pins. a/d converter interrupt the device contains an internal a/d converter with its own interrupt function. for an a/d interrupt to occur, the corresponding a/d interrupt enable bit must be frst set. this is bit 1 in the mfi1c register and known as eadi. an a/d interrupt is generated when the a/d conversion process is complete, after which the related interrupt request fag, adf, which is bit 5 in the mfi1c register, will be set. the interrupt vector for the a/d interrupt is the multi-function interrupt located at 014h. therefore if the multi-function and a/d interrupt are enabled, the stack is not full and the a/d conversion completes, a subroutine call to location 014h will take place. the multi-function interrupt request fag mff1 will be reset automatically and the emi bit will be cleared to disable other interrupts. the a/d interrupt flag will not be reset automatically and needs to be reset manually by the application program. serial interface interrupt the device contains an internal serial interface with its own interrupt function. for a serial interface interrupt to occur, the corresponding serial interface interrupt enable bit must be frst set. this is bit 0 in the mfi1c register and known as esii. a serial interface interrupt is generated when a data reception or transmission is complete, after which the related interrupt request fag, sif, which is bit 4 in the mfi1c register, will be set. the interrupt vector for the serial interface interrupt is the multi-function interrupt, located at 014h. therefore if the multi-function and serial interface interrupt are enabled, the stack is not full and a serial interface data reception or transmission is complete, a subroutine call to location 014h will take place. the multi-function interrupt request fag mff1 will be reset automatically and the emi bit will be cl eared to disable other interrupts. the serial interface interrupt fag will not be reset automatically and needs to be reset manually by the application program.
rev 1.00 ?? ???i? 1?? ? 011 rev 1.00 ?5 ???i? 1?? ? 011 HT82A824R usb audio mcu programming considerations by disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request fag is set, it will remain in this condition in the interrupt control register until the corresponding interrupt is serviced or until the request fag is cleared by a software instruction. it is recommended that programs do not use the call subroutine instruction within the interrupt subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. all of these interrupts have the capability of waking up the processor when in the power down mode. only the program counter is pushed onto the stack. if the contents of the accumulator or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance. reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the frst program instruction. after this power-on reset, certain important internal registers will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the reset line is forcefully pulled low. in such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overfows and resets the microcontroller. all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the reset reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and externally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is frst applied to the microcontroller. as well as ensuring that the program memory begins execution from the frst memory address, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs.
rev 1.00 ?? ???i? 1?? ? 011 rev 1.00 ?5 ???i? 1?? ? 011 HT82A824R usb audio mcu although the microcontroller has an internal rc reset function, if the v dd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recommended that an external rc network is connected to the reset pin, whose additional time delay will ensure that the reset pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the reset line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the fgures stands for system start-up timer.
power-on reset timing chart for most applications a resistor connected between v dd and the reset pin and a capacitor connected between vss and the reset pin will provide a suitable external reset circuit. any wiring connected to the reset pin should be kept as short as possible to minimize any stray noise interference. basic reset circuit for applications that operate within an environment where more noise is present the enhanced reset circuit shown is recommended. enhanced reset circuit
rev 1.00 ?6 ???i? 1?? ? 011 rev 1.00 ?7 ???i? 1?? ? 011 HT82A824R usb audio mcu reset pin reset this type of reset occurs when the microcontroller is already running and the reset pin is forcefully pulled low by external hardware such as an external switch. in this case as in the case of other reset, the program counter will reset to zero and program execution initiated from this point.

res reset timing chart low voltage reset - lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a confguration option. if the supply voltage of the device drops to within a range of 0.9v~vlvr such as might occur when changing the battery, the lvr will automatically reset the device internally. the lvr includes the following specifcations: for a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~vlvr must exist for greater than the value tlvr specifed in the a.c. characteristics. if the low voltage state does not exceed 1ms, the lvr will ignore it and will not perform a reset function. low voltage reset timing chart watchdog time-out reset during normal operation the watchdog time-out reset during normal operation is the same as a hardware reset pin reset except that the watchdog time-out fag to will be set to 1 wdt time-out reset during normal operation timing chart watchdog time-out reset during power down the watchdog time-out reset during power down is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to 0 and the to fag will be set to 1. refer to the a.c. characteristics for tsst details. wdt time-out reset during power down timing chart
rev 1.00 ?6 ???i? 1?? ? 011 rev 1.00 ?7 ???i? 1?? ? 011 HT82A824R usb audio mcu reset initial conditions the different types of reset described affect the reset fags in different ways. these fags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the power down function or watchdog timer. the reset fags are shown in the table: to pdf reset conditions 0 0 res ?eset du?ing ?owe?-on u u res o? lvr ?eset du?ing no?ma? o?e?ation 1 u wdt time-out ?eset du?ing no?ma? o?e?ation 1 1 wdt time-out ?eset du?ing powe? down note: u stands for unchanged. the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset p?og?am counte? reset to ze?o inte??u?ts ??? inte??u?ts wi?? be disab?ed wdt c?ea? afte? ?eset? wdt begins counting time ?/event counte? time ? counte? wi?? be tu? ned off in?ut/out?ut po?ts i/o ?o?ts wi?? be setu? as in?uts stack pointe? stack pointe? wi?? ?oint to the to? of the stack the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will refect the situation for the larger package type. the states of the registers are summarized in the table. register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) tmr0h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx tmr0l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx tmr0c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu 00-0 1000 00-0 1000 tmr1h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx tmr1l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx tmr1c 00-0 1-- 00-0 1-- 00-0 1-- 00-0 1-- uu-u u-- 00-0 1-- 00-0 1-- p?og?am counte? 000h 000h 000h 000h 000h 000h 000h mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ?cc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
rev 1.00 ?8 ???i? 1?? ? 011 rev 1.00 ?9 ???i? 1?? ? 011 HT82A824R usb audio mcu register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu st ? tus -00 xxxx -1u uuuu -uu uuuu -01 uuuu -11 uuuu -uu uuuu -01 uuuu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 intc1 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu 0000 0111 0000 0111 p? 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 p? c 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 intc1 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 tbhp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu usvc 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ? wr 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 st ?ll 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 misc 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 setio xxxx x010 xxxx x010 xxxx x010 xxxx x010 xxxx x010 xxxx x010 xxxx x010 fifo0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo? xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo? xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 d?c_limit_l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 d?c_limit_h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 d?c_wr xxxx 0xxx xxxx 0xxx xxxx 0xxx xxxx 0xxx xxxx uxxxx xxxx 0xxx xxxx 0xxx usc 1000 0000 uuxx uuuu 10xx 0000 10xx 0000 10xx uuuu 1000 0u00 1000 0u00 usr 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 00uu 0000 00uu 0000 ucc 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0u00 u000 0u00 u000 sies 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0u00 u000 0u00 u000 pfdc 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0uuu 0000 0uuu 0000 pfdd 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0uuu 0000 0uuu 0000 sbcr 0110 0000 0110 0000 0110 0000 0110 0000 uuuu uuuu uuuu uuuu uuuu uuuu sbdr uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mode_ctrl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0uuu 0000 0uuu 0000 0uuu pl? y_d? t ?l_l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu pl? y_d? t ?l_h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu pl? y_d? t ?r_l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu
rev 1.00 ?8 ???i? 1?? ? 011 rev 1.00 ?9 ???i? 1?? ? 011 HT82A824R usb audio mcu register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) pl? y_d? t ?r_h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu p ?_w ?ke_ctrl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu ?drl xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu ?drh xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu ?dcr 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu uuuu uuuu uuuu uuuu ?csr 1--- --00 1--- --00 1--- --00 1--- --00 u--- --uu u--- --uu u--- --uu mfi1c 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 usb_st ? te 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu fifo5 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo6 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 ? ttenu_ctrl_l 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu ? ttenu_ctrl_r 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu usf 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 usr1 0000 1011 0000 1011 0000 1011 0000 1011 uuuu uuuu uuuu uuuu uuuu uuuu ucr1 0000 00x0 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu uuuu uuuu uuuu uuuu ucr? 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu txr/rxr xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu brg xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pwmc 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu pwm0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pwm1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu note: * stands for warm reset u stands for unchanged x stands for unknown - stands for undefned
rev 1.00 50 ???i? 1?? ? 011 rev 1.00 51 ???i? 1?? ? 011 HT82A824R usb audio mcu oscillator the device use crystal oscillator as the system clock source. two types of crystal system clock frequencies can be selected while various clock source options for the watchdog timer are provided for maximum fexibility. system crystal/ceramic oscillator for the 12mhz crystal oscillator confgurations, the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation. for the 6mhz crystal oscillator confguration the addition of two small value capacitors are required. the sysclk bit in the ucc register determines the system frequency selection. crystal c1, c2 6mhz c?ysta? ?? ?f 1?mhz c?ysta? nc watchdog timer oscillator the wdt oscillator is a fully self-contained free running on-chip rc oscillator with a typical period of 65s at 5v requiring no external components. when the device enters the power down mode, the system clock will stop running but the wdt oscillator continues to free-run and to keep the watchdog active. however, to preserve power in certain applications the wdt oscillator can be disabled via a confguration option.
rev 1.00 50 ???i? 1?? ? 011 rev 1.00 51 ???i? 1?? ? 011 HT82A824R usb audio mcu power down mode and wake-up power down mode all of the holtek microcontrollers have the ability to enter a power down mode. when the device enters this mode, the normal operating current, will be reduced to an extremely low standby current level. this occurs because when the device enters the power down mode, the system oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. this feature is extremely important in application areas where the microcontroller must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. entering the power down mode there is only one way for the device to enter the power down mode and that is to execute the halt instruction in the application program. when this instruction is executed, the following will occur: the system oscillator will stop running and the application program will stop at the halt instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the wdt oscillator. the wdt will stop if its clock source originates from the system clock. the i/o ports will maintain their present condition. in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. standby current considerations as the main reason for entering the power down mode is to keep the current consumption of the mcu to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimized. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. care must also be taken with the loads, which are connected to i/os, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the watchdog timer internal oscillator.
rev 1.00 5? ???i? 1?? ? 011 rev 1.00 53 ???i? 1?? ? 011 HT82A824R usb audio mcu wake-up after the system enters the power down mode, it can be woken up from one of various sources listed as follows: an external reset an external falling or rising edge on port a an external falling edge on port b~port c a system interrupt a wdt overfow if the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a wdt overfow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup via an individual configuration option to permit a negative (or positive) transition on the pin to wake-up the system. when a port a pin wake-up occurs, the program will resume execution at the instruction following the hal t instruction. each pin on can be setup via an individual confguration option to permit a negative transition on the pin to wake-up the system. port a has an addition function, controlled via the pa_wake_ ctrl register in the data memory, allowing either a negative or positive edge to initiate a wake- up function. any external pin wake-up will cause the system to resume execution at the instruction following the halt instruction. if the system is woken up by an interrupt, then two possible situations may occur. the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the halt instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request fag is set to 1 before entering the power down mode, the wake-up function of the related interrupt will be disabled. no matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal system operation resumes. however, if the wake-up has originated due to an interrupt, the actual interrupt subroutine execution will be delayed by an additional one or more cycles. if the wake-up results in the execution of the next instruction following the halt instruction, this will be executed immediately after the 1024 system clock period delay has ended.
rev 1.00 5? ???i? 1?? ? 011 rev 1.00 53 ???i? 1?? ? 011 HT82A824R usb audio mcu watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. it operates by providing a device reset when the wdt counter overfows. the wdt clock is supplied by two sources selected by confguration option: its own self contained dedicated internal wdt oscillator or f sys /4. note that if the wdt confguration option has been disabled, then any instruction relating to its operation will result in no operation. the internal wdt oscillator has an approximate period of 65s at a supply voltage of 5v. if selected, it is frst divided by 256 via an 8-stage counter. note that this period can vary with v dd , temperature and process variations. for longer wdt time-out periods the wdt prescaler can be utilized. by writing the required value to bits 0, 1 and 2 of the wdts register, known as ws0, ws1 and ws2, longer time-out periods can be achieved. with ws0, ws1 and ws2 all equal to 1, the division ratio is 1:128 which gives a maximum time-out period. a confguration option can select the instruction clock, which is the system clock divided by 4, as the wdt clock source instead of the internal wdt oscillator. if the instruction clock is used as the clock source, it must be noted that when the system enters the power down mode, as the system clock is stopped, then the wdt clock source will also be stopped. therefore the wdt will lose its protecting purposes. in such cases the system cannot be restarted by the wdt and can only be restarted using external signals. for systems that operate in noisy environments, using the internal wdt oscillator is therefore the recommended choice. under normal program operation, a wdt time-out will initialise a device reset and set the status bit to. however, if the system is in the power down mode, when a wdt time-out occurs, only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the wdt and the wdt prescaler. the first is an external hardware reset, which means a low level on the reset pin, the second is using the watchdog software instructions and the third is via a halt instruction. there are two methods of using software instructions to clear the watchdog timer, one of which must be chosen by confguration option. the frst option is to use the single clr wdt instruction while the second is to use the two commands clr wdt1 and clr wdt2. for the frst option, a simple execution of clr wdt will clear the wdt while for the second option, both clr wdt1 and clr wdt2 must both be executed to successfully clear the wdt. note that for this second option, if clr wdt1 is used to clear the wdt, successive executions of this instruction will have no effect, only the execution of a clr wdt2 instruction will clear the wdt. similarly, after the clr wdt2 instruction has been executed, only a successive clr wdt1 instruction can clear the watchdog timer.
rev 1.00 5? ???i? 1?? ? 011 rev 1.00 55 ???i? 1?? ? 011 HT82A824R usb audio mcu

? ? ? ? ? ? ? watchdog timer register
?? ? ? ?? - ? ? ? ? ? ? ?? ?? ? watchdog timer
rev 1.00 5? ???i? 1?? ? 011 rev 1.00 55 ???i? 1?? ? 011 HT82A824R usb audio mcu usb function the device includes a usb 1.1 interface which can be used for data application data transfer. six endpoints are included in the usb function of this device. usb interface the usb interface in the HT82A824R device has 6 endpoints, known as ep0~ep2, ep4~ep6. endpoint 0, ep0, is used for control transfer. endpoints ep1 and ep4 are for interrupt transfer, while ep2 supports the isochronous out transfer. ep5 and ep6 are for bulk (or interrupt) transfer. a set of registers stored in the data memory is used for overall control of the usb function. these control registers include, usc, usr, ucc, awr, stall, sies and misc. there are also six fifo registers with the names fifo0~fifo2, fifo4~fifo6. the size of each fifo is as follows: fifo0-8 bytes, fifo1-8 bytes, fifo2-384 bytes, fifo4-32 bytes, fifo5-32 bytes and fifo6-64 bytes giving a total of 528 bytes. the urd bit, which is bit7 of the usc register is the usb reset signal control function defnition bit. usb interface registers the usb setup, data management and endpoint control in the device is controlled via a series of registers in the data memory usc register the usc register is the register for the overall control of the usb function. the initial status of this register is 80h.
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? ? ? ? ?? ? ?? ?- -? ? ?? ? ? ? ? ?? ?? usb control register - usc
rev 1.00 56 ???i? 1?? ? 011 rev 1.00 57 ???i? 1?? ? 011 HT82A824R usb audio mcu further explanation of each of the bits is given below: susp the susp bit is the usb suspend indicator bit. when this read-only bit is set to 1 by the sie, it indicates that the usb bus has entered the suspend mode. the usb interrupt is also triggered when this bit changes from low to high. rmwk the rmwk read/write bit is the usb remote wake-up command. it is set by the mcu to allow the usb host to leave the suspend mode after an external wake-up. urst the urst read/write bit is the usb reset indication bit. this bit is set and cleared by the usb sie and indicates a usb reset event on the usb bus. when this bit is set to 1, this indicates that a usb reset has occurred and that a usb interrupt will be generated. resume the resume read only bit is used to indicate that the usb has left the suspend mode. when the usb has left the suspend mode, this read-only bit is set to 1 by the sie. when the resume bit is set by sie, an interrupt will be generated to wake-up the mcu. in order to detect the suspend state, the mcu should set the usbcken bit and clear susp2 in the ucc register, to enable the sie detect function. the resume bit will be cleared when susp goes to 0. when the mcu is detecting the susp, the condition of the resume bit, which will wake-up the mcu, should be noted and taken into consideration. v33c the v33c read/write bit is the control bit for the internally generated 3.3v supply for the usb interface. pllenb the pllenb read/write bit is the control bit for the internal phase locked loop function. crcfg the crcfg read/write bit is the crc error condition failure fag. the crcfg bit will be set by the hardware however the crcfg bit needs to be cleared using frmware. urd the urd read/write bit is the usb reset signal control function defnition bit.
rev 1.00 56 ???i? 1?? ? 011 rev 1.00 57 ???i? 1?? ? 011 HT82A824R usb audio mcu usr register the usr register is the usb endpoint interrupt status register and is used to indicate which endpoint is accessed and to select the usb bus. the endpoint request fags, ep0f, ep1f, ep2f, ep4f, ep5f and ep6f are used to indicate which endpoints are accessed. if an endpoint is accessed, the related endpoint request fag will be set to 1 and the usb interrupt will be generated if the usb interrupt is enabled and the stack is not full. when the active endpoint request fag is serviced, the endpoint request fag has to be cleared to 0 by software.

usb endpoint status register - usr further explanation of each of the bits is given below: ep0f~ep2f, ep4f~ep6f the ep0f~ep2f, ep4f~ep6f read/write bits are set by the sie to indicate whether the associated endpoint has been accessed and a usb interrupt generated. after the interrupt has been serviced the bits should be cleared by the application program.
rev 1.00 58 ???i? 1?? ? 011 rev 1.00 59 ???i? 1?? ? 011 HT82A824R usb audio mcu ucc register the ucc register is the system clock control register and is used to select the clock that is used in the mcu. this register consists of a usb clock control bit, usbcken, a second suspend mode control bit, susp2, and a system clock selection bit, sysclk. the register also controls the endpoint selection, which is determined by bits eps0, eps1 and eps2.
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? - ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ?? ? ?? ?? ? ? ? ? ? ?? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ??? ? ? ? ? ?? ? ? ? system clock control register - ucc further explanation of each of the bits is given below: eps0~eps2 these three read/write bits are for the endpoint fifo selection. it should be noted that isochronous endpoints 2 is implemented in hardware, therefore fifo2 cannot be read from or written to using frmware. usbcken the usbcken read/write bit enables the usb clock susp2 the susp2 read/write bit is the second suspend bit and is used to select a power reducing function when the device is in the suspend mode. in the normal mode this bit should be cleared to zero. f sys 16mhz this read/write bit is used to determine if the system clock is derived from an external oscillator or from the internal pll 16mhz clock. oscclk the oscclk read/write bit is used to determine if the oscillator clock is either 6mhz or 12mhz.
rev 1.00 58 ???i? 1?? ? 011 rev 1.00 59 ???i? 1?? ? 011 HT82A824R usb audio mcu awr register the awr register is used to store the current usb device address and also for control of the remote wake-up function. the initial value of the awr register is 00h. the address value extracted from the usb command must not be loaded into this register until the setup stage has fnished.
? ? ? ? ? ? - device address register - awr stall register the stall register shows whether the corresponding endpoint has operated correctly or not. as soon as the endpoint has operated incorrectly, the related read/write bit in the stall has to be set to 1. the stall register will be cleared by a usb reset signal and a setup token event. the initial value of the stall register is 00h.

?? ? ? ? ? ? ?? ? endpoint stall register - stall
rev 1.00 60 ???i? 1?? ? 011 rev 1.00 61 ???i? 1?? ? 011 HT82A824R usb audio mcu sies register the sies register is the setup register for the serial interface engine.
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? ?? ? ? ? ? ? ? ? ?? serial interface setup register - sies further explanation of each of the bits is given below: aset the read/write aset bit is used to confgure the sie to automatically change the device address to the value presently stored in the awr register. when this bit is set to 1 by, the sie will update the device address with the value stored in the awr register after the pc host has successfully read the data from the device with an in operation. otherwise, when this bit is cleared to 0, the sie will update the device address immediately after an address is written to the awr register. therefore in order to work properly, the program has to clear this bit after a next valid setup token is received. err the read/write err bit is used to indicate that errors have occurred when the fifo is accessed. this bit is set by sie and should be cleared by the program. this bit is used for all endpoints. out the read/write out bit is used to indicate the reception of an out token, except for the out zero length token. the device will clear this bit after the out data has been read. also, this bit will be cleared by the sie after the next valid setup token is received. in the read only in bit is used to indicate that the current usb receiving signal from pc host is an in token.
rev 1.00 60 ???i? 1?? ? 011 rev 1.00 61 ???i? 1?? ? 011 HT82A824R usb audio mcu nak this read only bit is used to indicate that the sie has transmitted a nak signal to the host in response to the pc host in or out token. crcf the crcf read/write is an error condition failure fag that includes crc, pid and no integrate token error. crcf will be set by the hardware but needs to be cleared by the frmware. eot the eot read only read only fag is the token package active fag. note that this fag is active low. nmi the read/write nmi bit is the nak token interrupt mask fag. if this bit set, when the device sends a nak token to the host, the interrupt will be disabled. otherwise if this bit is cleared, when the device sends a nak token to the host, it will enter the interrupt subroutine.
rev 1.00 6? ???i? 1?? ? 011 rev 1.00 63 ???i? 1?? ? 011 HT82A824R usb audio mcu misc register the misc register combines command and status to control the desired endpoint fifo action and to show the status of the desired endpoint fifo. the misc register will be cleared by a usb reset signal.

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? ? ? ? - - - ?? ? ? ? ? ? ? ? ?? ? ? ?? ?? ? ? ?? ? ?? miscellaneous register - misc further explanation of each of the bits is given below: request the read/write request, if set high, can request the fifo after the corresponding status has been set. when fnished this bit must be set low tx the read/write tx bit represents the direction and mcu access transition end. when set high, the mcu desires to write data to the fifo. after fnishing, this bit must be set low before terminating the request to represent a transition end. for an mcu read operation, this bit must be set low and then high after fnishing. clear the read/write clear bit mcu is used to request a fifo clear, even if the fifo is not ready. after clearing the fifo, the usb interface will send a force_tx_err to tell the host that data under-run if the host wants to read data. iso_out_en the read/write iso_out_en bit enables the isochronous out pipe interrupt. setcmd the read/write setcmd bit is used to show that the data in the fifo is a setup command. the bit will remain in the same state until the following data enters the fifo. ready the read only ready bit is used to indicate that the desired fifo is ready. len0 the read only len0 bit is used to indicate that the host has sent a 0-sized packet to the mcu. this bit must be cleared by a read action to the corresponding fifo.
rev 1.00 6? ???i? 1?? ? 011 rev 1.00 63 ???i? 1?? ? 011 HT82A824R usb audio mcu setio register the setio register is used to setup the endpoints to either input or output pipe type. the data token toggle bit is also contained within this register. note that for usb definition, when the host sends a set confguration, the data pipe should send data0, about the data toggle, frst. therefore, when the device receives a set confguration setup command, the user needs to toggle this bit as the following data will send data0 frst. it is only required to set the data pipe as an input pile or output pile. the purpose of this function is to avoid the host sending an abnormal in or out token and disabling the endpoint. all bits are read/write.

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? usb endpoint setup in/out pipe register - setio
rev 1.00 6? ???i? 1?? ? 011 rev 1.00 65 ???i? 1?? ? 011 HT82A824R usb audio mcu usb_state register this register is used to indicate the error state due to se0 or se1 noise, the usbd- and usbd+ input signals and the i 2 s output control. the se0 and se1 bits are set by the sie and cleared with the program. usb-state register b0 sclk clock selection sclk1 sclk0 0 0: mclk/4 0 1: mclk/2 1 x: mclk se0 noise detection 1: noise detected in usb bus 0: noise not detected se1 noise detection 1: noise detected in usb bus 0: noise not detected usbd- input usbd+ input 0: left justified mode 1: i 2 s mode i 2 s output enable control bit 1: i 2 s output enable (the pa4~pa7 are as i 2 s output pins) 0: i 2 s output disable (the pa4~pa7 are as i/o pins) - default "0" b7 usbdp usbdn se1 se0 sclk1 sclk0 i 2 s_out_en i 2 s_format usb state register - usb-state the pa4~pa7 are pin-shared with i 2 s output pins. the following table illustrates the corresponding pin assignment. when the i 2 s_out_en bit is set to high, that will enable the i 2 s output function and the pa4~pa7 will force to be the i 2 s data output pins by hardware. pa4~pa7 i 2 s pin assignment (i 2 s_out_en=1) pin name i 2 s pins i/o description p ?? mclk o i 2 s maste? c?ock p? 5 sclk o i 2 s se?ia? c?ock p? 6 lrck o i 2 s left/right c?ock p? 7 sd ?t? o i 2 s se?ia? data the HT82A824R provided the i 2 s output mode which is left justifed or i 2 s 16-bit mode and the output pins can be connected to an external i 2 s d/a converter to generate the audio signal. when the i 2 s_out_en bit is set to high, the i 2 s output will be enabled at the same time. the following diagram illustrates the i 2 s data format.

left justifed 16-bit mode

i 2 s 16-bit mode
rev 1.00 6? ???i? 1?? ? 011 rev 1.00 65 ???i? 1?? ? 011 HT82A824R usb audio mcu suspend wake-up remote wake-up the device includes a suspend mode. if there is no signal on the usb bus for over 3ms, the device will enter a suspend mode. when this happens, the suspend bit, which is bit 0 of the usc register, will be set to 1 and a usb interrupt will be generated to indicate that the device should jump to the suspend state to meet the requirements of the usb suspend current spec. in order to meet the requirements of the suspend current, the program should disable the usb clock by clearing the usbcken bit, which is bit3 of the ucc register, to 0. the suspend current can be further decreased by setting the susp2 bit, which is bit4 of the ucc register. when the resume signal is sent out by the host, the HT82A824R will be woken up the by the usb interrupt and the resume bit, which is bit 3 of the usc register, will be set. in order to make the device operate correctly, the program must set the usbcken bit and clear the susp2 bit. since the resume signal will be cleared before the idle signal is sent out by the host and the suspend bit, will change to 0. therefore when the mcu is detecting the suspend line, the condition of the resume line should be noted and taken into consideration. the following shows the related timing of this operation: the device contains a remote wake up function which can wake-up the usb host by sending a wake-up pulse through the rmwk bit, which is bit 1 of the usc register. once the usb host receives a wake-up signal from the device, it will send a resume signal to the device. the following shows the related timing:

usf register this register is used to indicate the data ram bank1~4 are assigned for usb audio data or 12- bit a/d converted data, the a/d bias setting, the ram bank1~4 data mode selection and the data loaded status.
rev 1.00 66 ???i? 1?? ? 011 rev 1.00 67 ???i? 1?? ? 011 HT82A824R usb audio mcu

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? ? ? ? ?? ? ? ? ?? usb speaker flag register - usf when the data_mode bit in usf register is cleared to low, the data ram bank1~4 are assigned to the usb audio data. the dma controller will fetch the usb audio data to ram bank1~4 sequentially via the sampling frequency 48khz (play_mode=0) or 44.1khz (play_mode=1). if the startbit bit is set to high will enable the dma controller and if the loading process is completed, the fullbit bit will be set to high by hardware. fu??bit ==1 sta?tbit = 1 n y sta?tbit = 0 read r?m bank 1 ~ ? end flow chart of reading ram bank 1~4 (data_mode=0)
rev 1.00 66 ???i? 1?? ? 011 rev 1.00 67 ???i? 1?? ? 011 HT82A824R usb audio mcu when the data_mode bit in usf register is set to high, the data ram bank1~4 are assigned to the adc converted data. the dma controller will fetch the adc converted data to ram bank1~4 sequentially via the sampling frequency fsys/256. if the startbit bit is set to high will enable the dma controller and if the loading process is completed, the fullbit bit will be set to high by hardware. if the adc interrupt related control bits are enabled, the adc interrupt will happen as every one sample conversion process is completed. the following block diagram illustrates the functional blocks for the data fetching process from the adc to the data ram bank1~4. ram bank1~bnak4 ?n0 datamode=1 ?udio in?ut (l) ?n1 ?udio in?ut (r) 12-bit adc m u x dma controller bias circuit bi?s_ctrl
rev 1.00 68 ???i? 1?? ? 011 rev 1.00 69 ???i? 1?? ? 011 HT82A824R usb audio mcu the following fow chart illustrates the procedure for the data fetching process from the adc to the data ram bank1~4. fu??bit=1 sta?tbit=1 n y sta?tbit=0 read r?m bank 1~? end note: 1.?fte? setting the sta?tbit to high by softwa?e? the dm? cont?o??e? wi?? sta?t to fetch the ?dc conve?ted data to r?m bank1~?. ?.if the 51? bytes data a?e fetched to the r?m bank1~?? the fu??bit bit wi?? be set to high by ha?dwa?e. 3.the ?dc c?ock sou?ce wi?? be fo?ced to be the system c?ock f sys . disab?e ?dc inte??u?t f/w setting h/w dm? enab?e bias ci?cuit powe? u? 1?-bit ?/d conve?te? data_mode=1 flow chart of reading ram bank 1~4 (data_mode=1)
rev 1.00 68 ???i? 1?? ? 011 rev 1.00 69 ???i? 1?? ? 011 HT82A824R usb audio mcu audio data format if the data_mode is cleared to low, the ram bank1~4 data is from usb audio data. bank1~bank4 audio data format (16 bit 8 bit): 15 1? 1 0 13... ? bank 1 ~ bank ? usb ?udio data fo?mat ( 16 bit 8 bit ) 15 13 8 7 1?...9 o?igina? 16 bit ?udio data ( ? ' s com??ement ) t?uncate 16 bit ?udio data to 8 - bit if the data_mode is set to high, the ram bank1~4 data is from adc converted data via an0 and an1 channels. bank1~bank4 audio data format (12 bit 8 bit): bank 1 ~ bank ? data fo?mat ( 1? bit 8 bit ) o?igina? 1? bit ? / d data ( ? ' s com??ement ) t?uncate 1? bit ? / d data to 8 - bit 11 10 1 0 9 ... ? 11 10 5 ? 9 ...6 modese?ect=0 (s?ct?um? (r+l)/?) r?m bank 1 r?m bank ? r?m bank 3 r?m bank ? 1?8 bytes 1?8 bytes 1?8 bytes 1?8 bytes 51? sam??es data_mode=0 or data_mode=1 r?m bank 1 r?m bank ? r?m bank 3 r?m bank ? 1?8 bytes? left channe? 1?8 bytes? left channe? 1?8 bytes? right channe? 1?8 bytes? right channe? ?56 left channe? sam??es ?56 right channe? sam??es modese?ect=1 (l/r) data_mode=0 or data_mode=1
rev 1.00 70 ???i? 1?? ? 011 rev 1.00 71 ???i? 1?? ? 011 HT82A824R usb audio mcu usb speaker volume control the speaker output volume as well as the speaker mute/un-mute function are controlled by the usb speaker volume control usvc register. the volume range can be set between a range of 6db to -32db by software. the relationship between the usvc volume control bits and the amplifcation or attenuation values are shown in the volume control table. the mute control will be enabled when the muteb bit is low and both the dac and the power amplifer will be muted.

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? usb speaker volume control register - usvc result (db) usvc result (db) usvc result (db) usvc result (db) usvc 6 000_1100 -? 111_1100 -10 110_1100 -?? 101_1100 5.5 000_1011 -?.5 111_1011 -10.5 110_1011 -?5 101_1011 5 000_1010 -3 111_1010 -11 110_1010 -?6 101_1010 ?.5 000_1001 -3.5 111_1001 -11.5 110_1001 -?7 101_1001 ? 000_1000 -? 111_1000 -1? 110_1000 -?8 101_1000 3.5 000_0111 -?.5 111_0111 -13 110_0111 -?9 101_0111 3 000_0110 -5 111_0110 -1? 110_0110 -30 101_0110 ?.5 000_0101 -5.5 111_0101 -15 110_0101 -31 101_0101 ? 000_0100 -6 111_0100 -16 110_0100 -3? 101_0100 1.5 000_0011 -6.5 111_0011 -17 110_0011 C C 1 000_0010 -7 111_0010 -18 110_0010 C C 0.5 000_0001 -7.5 111_0001 -19 110_0001 C C 0 000_0000 -8 111_0000 -?0 110_0000 C C -0.5 111_1111 -8.5 110_1111 -?1 101_1111 C C -1 111_1110 -9 110_1110 -?? 101_1110 C C -1.5 111_1101 -9.5 110_1101 -?3 101_1101 C C speaker volume control table note: speaker mute control mute =0: mute speaker output. mute =1: normal. fifo registers fifo0~fifo6 (28h~2ch, 4bh~4ch) usb endpoint accessing registers defnitions registers r/w power-on function fifo0~fifo6 r/w xxh epi accessing ? egiste ? C epsx bits in the ucc ? egiste ? . (i = 0~6). when an end?oint is disab?ed? th co??es?onding accessing ?egiste? shou?d be disab?ed.
rev 1.00 70 ???i? 1?? ? 011 rev 1.00 71 ???i? 1?? ? 011 HT82A824R usb audio mcu dac limit registers the dac_limit_l and dac_limit_h registers are used to defne the 16-bit dac output limits. the values in the dac_limit_l and dac_limit_h registers are unsigned values. if the 16-bit data from the host exceeds that of the range defned by the two dac_limit_l and dac_limit_h registers then the output digital code to dac will be clamped within these register values. dac_limit_l d?c out?ut ?imit ?ow byte dac_limit_h d?c out?ut ?imit high byte example to set the dac output limit values: ;----------------------------------------------------------- ; set dac limit value=ff00h ;----------------------------------------------------------- clr [02dh] ; set dac limit low byte=00h set [02eh] ; set dac limit high byte=ffh ;----------------------------------------------------------- in order to prevent a popping noise from the speaker output, the power amplifer should output a value of v dd /2, which means a value of 8000h should be sent to the dac during the initial power on state. generating a pulse on the dac_wr_trig bit will write the values into the dac. if the dac_wr_trig, bit 3 of the dac_wr register, is already high then clearing the dac_wr_trig bit, will write the values into the dac_limit_l and dac_limit_h registers for the dac.
dac write and record source register dac_wr

note: in the dac write data mode (high nibble of wdts register is 0101b), the dac_limit_l and dac_ limit_h registers will be the 16-bit dac input data register at the falling edge of dac_wr_trig. otherwise, these two registers are used to defne the 16-bit dac output limit (repeated below).
rev 1.00 7? ???i? 1?? ? 011 rev 1.00 73 ???i? 1?? ? 011 HT82A824R usb audio mcu example to avoid popping noise: system_initial: ;----------------------------------------------------------- ; avoid pop noise ;----------------------------------------------------------- mov a,wdts mov fifo_temp,a ;save wdts value mov a,00001111b andm a,wdts mov a,01010000b orm a,wdts ;enter dac write data mode, high nibble of wdts=0101b clr [02dh] ;set dac data low byte=00h mov a,80h mov [02eh],a ;set dac data high byte=80h nop ;write 8000h to dac set [02fh].3 nop clr [02fh].3 nop ;----------------------------------------------------------- mov a,fifo_temp ;restore wdts value mov wdts,a ;quit dac write data mode ;----------------------------------------------------------- spi serial interface the device includes a single spi serial interface. the spi interface is a full duplex serial data link, originally designed by motorola, which allows multiple devices connected to the same spi bus to communicate with each other. the devices communicate using a master/slave technique where only the single master device can initiate a data transfer. a simple four line signal bus is used for all communication. spi interface communication four lines are used for spi communication known as sdi - serial data input, sdo - serial data output, sck - serial clock and scs - slave select. note that the condition of the slave select line is conditioned by the csen bit in the sbcr control register. if the csen bit is high then the scs line is active while if the bit is low then the scs line will be in a foating condition. the following timing diagram depicts the basic timing protocol of the spi bus. spi registers there are two registers associated with the spi interface. these are the sbcr register which is the control register and the sbdr which is the data register. the sbcr register is used to setup the required setup parameters for the spi bus and also used to store associated operating fags, while the sbdr register is used for data storage. after power on, the contents of the sbdr register will be in an unknown condition while the sbcr register will default to the condition below: cks m1 m0 sben mls csen wcol trf 0 1 1 0 0 0 0 0 note that data written to the sbdr register will only be written to the txrx buffer, whereas data read from the sbdr register will actually be read from the register .
rev 1.00 7? ???i? 1?? ? 011 rev 1.00 73 ???i? 1?? ? 011 HT82A824R usb audio mcu spi bus enable/disable to enable the spi bus then csen=1 and sben=1, the sck, sdi, sdo and scs lines should all be zero, then wait for data to be written to the sbdr (txrx buffer) register. for the master mode, after data has been written to the sbdr (txrx buffer) register then transmission or reception will start automatically. when all the data has been transferred the trf bit should be set. for the slave mode, when clock pulses are received on sck, data in the txrx buffer will be shifted out or data on sdi will be shifted in. to disable the spi bus sck, sdi, sdo, scs foating. spi operation all communication is carried out using the 4-line interface for both master or slave mode. the timing diagram shows the basic operation of the bus.
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rev 1.00 7? ???i? 1?? ? 011 rev 1.00 75 ???i? 1?? ? 011 HT82A824R usb audio mcu
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?? ? ? ? - ? ? ?? ? ? ? ? ?? ? spi interface control register the sben bit determines if pins pc4~pc7 are used as normal i/o pins or as spi function pins. if this bit is high then the pins will be spi function pins and here pin scs will go low if csen = 1. if the bit is low then the pins will function as normal i/o pins. note that when sben = 1, then any pull-high resistors connected to pins pc4~pc7 will be disconnected therefore the user hardware should ensure that external pull-high resistors are added to the spi pins if necessary. if csen = 0 then the scs pin will be in a foating state. the spi clock polarity is controlled using the sio_cpol bit in the mode_ctrl register. if sio_ cpol = 1, then the rising edge will be selected. otherwise if sio_cpol = 0, the falling edge will be selected. the csen bit in the sbcr register controls the overall function of the spi interface. setting this bit high, will enable the spi interface by allowing the scs line to be active, which can then be used to control the spi interface. if the csen bit is low, the spi interface will be disabled and the scs line will be in a foating condition and can therefore not be used for control of the spi interface. the sben bit in the sbcr register must also be high which will chan ge the pin function from a standard i/o to an spi function pin. if in the master mode the sck line will be either high or low depending upon the clock polarity confguration option. if in the slave mode the sck line will be in a foating condition. if sben is low then the bus will be disabled. in the master mode the master will always generate the clock signal. the clock and data transmission will be initiated after data has been written to the sbdr register . in the slave mode, the clock signal will be received from an external master device for both data transmission or reception. the following sequences show the order to be followed for data transfer in both master and slave mode:
rev 1.00 7? ???i? 1?? ? 011 rev 1.00 75 ???i? 1?? ? 011 HT82A824R usb audio mcu master mode: ? step 1. select the clock source using the cks bit in the sbcr control register ? step 2. setup the m0 and m1 bits in the sbcr control register to select the master mode and the required baud rate. values of 00, 01 or 10 can be selected. ? step 3. setup the csen bit and setup the mls bit to choose if the data is msb or lsb frst, this must be same as the slave device. ? step 4. setup the sben bit in the sbcr control register to enable the spi interface. ? step 5. for write operations: write the data to the sbdr register , which will actually place the data into the txrx buffer. then use the sck and scs lines to output the data. after this goto to step 6. for read operations: the data transferred in on the sdi line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the sbdr register. ? step 6. check the wcol bit, if set high then a collision error has occurred so return to step5. if equal to zero then go to the following step. ? step 7. check the trf bit or wait for an spi serial bus interrupt. ? step 8. read data from the sbdr register. ? step 9. clear trf. ? step10. goto step 5. slave mode: ? step 1. the cks bit has a dont care value in the slave mode. ? step 2. setup the m0 and m1 bits to 00 to select the slave mode. the cks bit is dont care. ? step 3. setup the csen bit and setup the mls bit to choose if the data is msb or lsb frst, this must be same as the master device. ? step 4. setup the sben bit in the sbcr control register to enable the spi interface. ? step 5. for write operations: write data to the sbcr register, which will actually place the data into the txrx register, then wait for the master clock and scs signal. after this, goto step 6. for read operations: the data transferred in on the sdi line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the sbdr register. ? step 6. check the wcol bit, if set high then a collision error has occurred so return to step5. if equal to zero then go to the following step. ? step 7. check the trf bit or wait for an spi serial bus interrupt. ? step 8. read data from the sbdr register. ? step 9. clear trf ? step10. goto step 5 sben =1 pc?~pc7 a?e spi function ?ins (?in scs wi?? go ?ow if csen=1). sben =0 pc?~pc7 a?e gene?a? ?u??ose i/o po?t ?ins (defau?t) note: 1. if sben=1, the pull-high resistor of pc4~pc7 will be disable. when this happens, the user should add external pull-high resistors to the spi related pins if necessary (ex: pin scs ). 2. if csen=0, the scs pin will enter a foating state.
rev 1.00 76 ???i? 1?? ? 011 rev 1.00 77 ???i? 1?? ? 011 HT82A824R usb audio mcu mls=1 ? msb shift first mls=0 ? lsb shift first ? mls=0 ? scsb sck sio_cpol=0 sio_ckeg=1 d7/d0 d6/d1 d5/d2 d4/d3 d3/d4 d2/d5 d1/d6 d0/d7 sdi d7/d0 d6/d1 d5/d2 d4/d3 d3/d4 d2/d5 d1/d6 d0/d7 sdo sio_cpol=1 sio_ckeg=1 sio_cpol=0 sio_ckeg=0 sio_cpol=1 sio_ckeg=0 error detection the wcol bit in the sbcr register is provided to indicate errors during data transfer. the bit is set by the serial interface but must be cleared by the application program. this bit indicates a data collision has occurred which happens if a write to the sbdr register takes place during a data transfer operation and will prevent the write operation from continuing. the bit will be set high by the serial interface but has to be cleared by the user application program. the overall function of the wcol bit can be disabled or enabled by a sio_wcol bit of mode_ctrl register. programming considerations when the device is placed into the power down mode note that data reception and transmission will continue. the trf bit is used to generate an interrupt when the data has been transferred or received. mode control register the mode_ctrl register is used to control dac and adc operation mode and spi function.
rev 1.00 76 ???i? 1?? ? 011 rev 1.00 77 ???i? 1?? ? 011 HT82A824R usb audio mcu

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? ? mode control register - mode_ctrl note: that the wcol and csen bits are in the sbcr register. spi usage example: spi_test: clr ucc.@ucc_sysclk ;12mhz sysclk set sio_csen ;spi chip select function enable set sio_cpol ;rising edge change data set sio_ckeg ;data output before serial clock edge ;master mode, sclk=fsio clr m1 clr m0 ;-------------- clr cks ;fsio=fsys/2 clr trf ;clear trf fag clr trf_int ;clear interrupt spi fag set mls ;msb shift frst set csen ;chip select enable set sben ;spi enable, scs will go low if polling_mode clr esii ;spi interrupt disable ;write into "write enable" instruction mov a,op_wren mov sbdr,a $0: snz trf jmp $0 clr trf else set esii ;spi interrupt enable ;write into "write enable" instruction mov a,op_wren mov sbdr,a $0: snz trf_int ;set at spi interrupt jmp $0 clr trf_int endif
rev 1.00 78 ???i? 1?? ? 011 rev 1.00 79 ???i? 1?? ? 011 HT82A824R usb audio mcu play data the play data for the device is contained in 4 play registers. the play interrupt will be activated when play data in the play_data registers is valid. the play_data registers will latch data until the next interrupt is generated. the dac play_data register contains an unsigned value with a range of 0~ffffh. the update rate for the play_data is 48khz, if the play_mode bit in the mode_ctrl register is equal to 0, or 44.1khz if the bit is equal to 1. all of the play registers are read only. name b7 b6 b5 b4 b3 b2 b1 b0 pl? y_d? t ?l_l pl_d7 pl_d6 pl_d5 pl_d? pl_d3 pl_d? pl_d1 pl_d0 pl? y_d? t ?l_h pl_d15 pl_d1? pl_d13 pl_d1? pl_d11 pl_d10 pl_d9 pl_d8 pl? y_d? t ?r_l pr_d7 pr_d6 pr_d5 pr_d? pr_d3 pr_d? pr_d1 pr_d0 pl? y_d? t ?r_h pr_d15 pr_d1? pr_d13 pr_d1? pr_d11 pr_d10 pr_d9 pr_d8 analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller, they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller, the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the device contains a 6-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. the following diagram shows the overall internal structure of the a/d converter, together with its associated registers. a/d converter data registers C adrl, adrh for the HT82A824R device, which has a 12-bit a/d converter, two registers are required, a high byte register, known as adrh, and a low byte register, known as adrl, to store the 12-bit analog to digital conversion value. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. note that only the high byte register adrh utilises its full 8-bit contents. the low byte register utilises only 4 bits of its 8-bit contents as it contains only the lowest bit of the 12-bit converted value. in the following tables, d0~d11 are the a/d conversion data result bits. register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ?drl d3 d? d1 d0 C C C C ?drh d11 d10 d9 d8 d7 d6 d5 d? a/d converter data register
rev 1.00 78 ???i? 1?? ? 011 rev 1.00 79 ???i? 1?? ? 011 HT82A824R usb audio mcu a/d converter control register C adcr to control the function and operation of the a/d converter, a control register known as adcr is provided. this 8-bit register defines functions such as the selection of which analog channel is connected to the internal a/d converter, power on/off the a/d converter, control the start function and monitoring the a/d converter end of conversion status. one section of this register contains the bits acs2~acs0 which defne the channel number. as each of the devices contains only one actual analog to digital converter circuit, each of the individual 6 analog inputs must be routed to the converter. it is the function of the acs2~acs0 bits in the adcr register to determine which analog channel is actually connected to the internal a/d converter.

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? ? ? a/d converter structure the adcr control register also contains the pcr2~pcr0 bits which determine power on/off the a/d converter and. if the pcr2~pcr0 bits are all set to zero, then the internal a/d converter circuitry will be powered off to reduce the power consumption. any other non-zero combination on the pcr2~pcr0 bits will power-on the the a/d converter will be power on which will consume a certain amount of power. the start bit in the adcr register is used to start and reset the a/d converter. when the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. when the start bit is brought from low to high but not low again, the eocb bit in the adcr register will be set to a 1 and the analog to digital converter will be reset. it is the start bit that is used to control the overall on/off operation of the internal analog to digital converter. the eocb bit in the adcr register is used to indicate when the analog to digital conversion process is complete. this bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle.
rev 1.00 80 ???i? 1?? ? 011 rev 1.00 81 ???i? 1?? ? 011 HT82A824R usb audio mcu a/d converter clock source register C acsr the clock source for the a/d converter, which originates from the system clock f sys , is frst divided by a division ratio, the value of which is determined by the adcs1 and adcs0 bits in the acsr register. although the a/d clock source is determined by the system clock f sys , and by bits adcs1 and adcs0, there are some limitations on the maximum a/d clock source speed that can be selected.

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? ? ? ? ? ? ? ? a/d converter clock source register a/d input pins all of the a/d analog input pins are independent analog inputs and not shared with other i/o pins. bits pcr2~pcr0 in the adcr register, not configuration options, determine whether the a/d converter is powered on or powered down. the avdd3 power supply pin is used as a separate pin for the a/d converter power supply while the avss3 pin is used as the a/d converter ground pin. the a/d converter reference is internally connected to the avdd3 power supply pin.
rev 1.00 80 ???i? 1?? ? 011 rev 1.00 81 ???i? 1?? ? 011 HT82A824R usb audio mcu initialising the a/d converter the internal a/d converter must be initialised in a special way. each time the a/d channel selection bits are modifed by the program, the a/d converter must be re-initialised. if the a/d converter is not initialised after the channel selection bits are changed, the eocb fag may have an undefned value, which may produce a false end of conversion signal. to initialise the a/d converter after the channel selection bits have changed, then, within a time frame of one to ten instruction cycles, the start bit in the adcr register must frst be set high and then immediately cleared to zero. this will ensure that the eocb fag is correctly set to a high condition. summary of a/d conversion steps the following summarizes the individual steps that should be ex ecuted in order to implement an a/d conversion process. step 1 select the required a/d conversion clock by correctly programming bits adcs1 and adcs0 in the acsr register. step 2 select which channel is to be connected to the internal a/d converter by correctly programming the acs2~acs0 bits which are also contained in the adcr register. step 3 select a/d converter power on or power down by programming the pcr2~pcr0 bits in the adcr register. note that this step can be combined with step 2 into a single adcr register programming operation. step 4 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master interrupt control bit, emi, in the intc0 interrupt control register must be set to 1, the multi-function 1 interrupt control bit, emf1i, in the intc1 register and the a/d converter interrupt bit, eadi, in the mfi1c register must also be set to 1. step 5 the analog to digital conversion process can now be initialised by setting the start bit in the adcr register from 0 to 1 and then to 0 again. note that this bit should have been originally set to 0. step 6 to check when the analog to digital conversion process is complete, the eocb bit in the adcr register can be polled. the conversion process is complete when this bit goes low. when this occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr register is used, the interrupt enable step above can be omitted.
rev 1.00 8? ???i? 1?? ? 011 rev 1.00 83 ???i? 1?? ? 011 HT82A824R usb audio mcu the following timing diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing.
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? ? ? ? ? - ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ?? ? ? ? ? ? ? ? a/d conversion timing the setting up and operation of the a/d converter function is fully under the control of the application program as there are no confguration options associ ated with the a/d converter. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. programming considerations when programming, special attention must be given to the a/d channel selection bits in the adcr register. this ability to reduce power by turning off the internal a/d function by clearing the a/d channel selection bits may be an important consideration in battery powered applications. another important programming consideration is that when the a/d channel selection bits change value the a/d converter must be re-initialised. this is achieved by pulsing the start bit in the adcr register immediately after the channel selection bits have changed state. the exception to this is where the channel selection bits are all cleared, in which case the a/d converter is not required to be re-initialised. a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the eocb bit in the adcr register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete.
rev 1.00 8? ???i? 1?? ? 011 rev 1.00 83 ???i? 1?? ? 011 HT82A824R usb audio mcu example: using an eocb polling method to detect the end of conversion for the HT82A824R. clr eadi ; disable adc interrupt mov a,00000001 b mov acsr,a ; setup the acsr register to select f sys /8 as the a/d ; clock mov a,00100000b ; setup the adcr register to power up the a/d ; converter mov adcr,a ; and select an0 to be connected to the a/d ; converter : ; the following start signal (0-1-0) must be issued : ; within 10 instruction cycles : start_conversion: clr start set start ; reset a/d clr start ; start a/d polling_eoc: sz eocb ; poll the adcr register eocb bit to detect end ; of a/d conversion jmp polling_eoc ; continue polling mov a,adrh ; read conversion result high byte value from the ; adrh register adr_buffer_h,a ; save result to user defned memory mov a,adrl ; read conversion result low byte value from the ; adrl register mov adr_buffer_l,a ; save result to user defned memory : : jmp start_conversion ; start next a/d conversion
rev 1.00 8? ???i? 1?? ? 011 rev 1.00 85 ???i? 1?? ? 011 HT82A824R usb audio mcu example: using an interrupt method to detect the end of conversion for the HT82A824R. clr eadi ; disable adc interrupt mov a,00000001b mov acsr,a ; setup the acsr register to select f sys /8 as the a/d ; clock mov a,00100000b ; setup the adcr register to power up the a/d ; converter mov adcr,a ; and select an0 to be connected to the a/d ; converter : ; the following start signal (0-1-0) must be issued : ; within 10 instruction cycles : start_conversion: clr adf ; clear adc interrupt request fag set emf1i ; multi function 1 interrupt enable set eadi ; enable adc interrupt set emi ; enable global interrupt clr start set start ; reset a/d clr start ; start a/d : : : ; adc interrupt service routine adc_isr: clr adf ; clear adc interrupt request fag mov acc_stack,a ; save acc to user defned memory mov a,status mov status_stack,a ; save status to user defned memory : : mov a,adrh ; read conversion result high byte value from the ; adrh register mov adr_buffer_h,a ; save result to user defned register mov a,adrl ; read conversion result low byte value from the ; adrl register mov adr_buffer_l,a ; save result to user defned register : : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defned memory mov a,
rev 1.00 8? ???i? 1?? ? 011 rev 1.00 85 ???i? 1?? ? 011 HT82A824R usb audio mcu a/d transfer function as the HT82A824R device contains a 12-bit a/d converter, their full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the voltage, this gives a single bit analog input value of v dd /4096. the following graphs show the ideal transfer function between the analog input value and the digitised output value for the a/d converters. note that to reduce the quantisation error, a 0.5 lsb offset is added to the a/d converter input. except for the digitised zero value, the subsequent digitised values will change at a point 0.5 lsb below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd level.

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? ideal a/d transfer function uart bus serial interface the HT82A824R device contains an integrated full-duplex asynchronous serial communications uart interface that enables communication with external devices that contain a serial interface. the uart function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. the uart function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. uart features the integrated uart function contains the following features: full-duplex, asynchronous communication 8 or 9 bits character length even, odd or no parity options one or two stop bits baud rate generator with 8-bit prescaler parity, framing, noise and overrun error detection support for interrupt on address detect (last character bit=1) separately enabled transmitter and receiver 2-byte deep fifo receive data buffer transmit and receive interrupts
rev 1.00 86 ???i? 1?? ? 011 rev 1.00 87 ???i? 1?? ? 011 HT82A824R usb audio mcu interrupts can be initialized by the following conditions: transmitter empty transmitter idle receiver full receiver overrun address mode detect uart external pin interfacing to communicate with an external serial interface, the internal uart has two external pins known as tx and rx. the tx pin is the uart transmitter pin, which can be used as a general purpose i/ o pin if the pin is not confgured as a uart transmitter, which occurs when the txen bit in the ucr2 control register is equal to zero. similarly, the rx pin is the uart receiver pin, which can also be used as a general purpose i/o pin, if the pin is not confgured as a receiver, which occurs if the rxen bit in the ucr2 register is equal to zero. along with the uarten bit, the txen and rxen bits, if set, will automatically setup these i/o pins to their respective tx output and rx input conditions and disable any pull-high resistor option which may exist on the rx pin. uart data transfer scheme the block diagram shows the overall data transfer structure arrangement for the uart. the actual data to be transmitted from the mcu is first transferred to the txr register by the application program. the data will then be transferred to the transmit shift register from where it will be shifted out, lsb frst, onto the tx pin at a rate controlled by the baud rate generator. only the txr register is mapped onto the mcu data memory, the transmit shift register is not mapped and is therefore inaccessible to the application program. data to be received by the uart is accepted on the external rx pin, from where it is shifted in, lsb first, to the receiver shift register at a rate controlled by the baud rate generator. when the shift register is full, the data will then be transferred from the shift register to the internal rxr register, where it is buffered and can be manipulated by the application program. only the rxr register is mapped onto the mcu data memory, the receiver shift register is not mapped and is therefore inaccessible to the application program. it should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate txr and rxr registers, only exists as a single shared register in the data memory. this shared register known as the txr/rxr register is used for both data transmission and data reception. uart status and control registers there are fve control registers associated with the uart function. the usr1, ucr1 and ucr2 registers control the overall function of the uart, while the brg register controls the baud rate. the actual data to be transmitted and received on the serial interface is managed through the txr/ rxr data registers.
rev 1.00 86 ???i? 1?? ? 011 rev 1.00 87 ???i? 1?? ? 011 HT82A824R usb audio mcu
uart data transfer scheme usr1 register the usr1 register is the status register for the uart, which can be read by the program to determine the present status of the uart. all fags within the usr1 register are read only. further explanation on each of the fags is given below: txif the txif fag is the transmit data register empty fag. when this read only fag is 0 it indicates that the character is not transferred to the transmit shift registers. when the fag is 1 it indicates that the transmit shift register has received a character from the txr data register. the txif fag is cleared by reading the uart status register (usr1) with txif set and then writing to the txr data register. note that when the txen bit is set, the txif fag bit will also be set since the transmit buffer is not yet full. tidle the tidle fag is known as the transmission complete fag. when this read only fag is 0 it indicates that a transmission is in progress. this fag will be set to 1 when the txif fag is 1 and when there is no transmit data, or break character being transmitted. when tidle is 1 the tx pin becomes idle. the tidle fag is cleared by reading the usr1 register with tidle set and then writing to the txr register. the fag is not generated when a data character, or a break is queued and ready to be sent. rxif the rxif fag is the receive register status fag. when this read only fag is 0 it indicates that the rxr read data register is empty. when the flag is 1 it indicates that the rxr read data register contains new data. when the contents of the shift register are transferred to the rxr register, an interrupt is generated if rie=1 in the ucr2 register. if one or more errors are detected in the received word, the appropriate receive-related fags nf, ferr, and/or perr are set within the same clock cycle. the rxif fag is cleared when the usr1 register is read with rxif set, followed by a read from the rxr register, and if the rxr register has no data available. ridle the ridle fag is the receiver status fag. when this read only fag is 0 it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. when the fag is 1 it indicates that the receiver is idle. between the completion of the stop bit and the detection of the next start bit, the ridle bit is 1 indicating that the uar t is idle.
rev 1.00 88 ???i? 1?? ? 011 rev 1.00 89 ???i? 1?? ? 011 HT82A824R usb audio mcu oerr the oerr fag is the overrun error fag, which indicates when the receiver buffer has overfowed. when this read only fag is 0 there is no overrun error. when the fag is 1 an overrun error occurs which will inhibit further transfers to the rxr receive data register. the fag is cleared by a software sequence, which is a read to the status register usr1 followed by an access to the rxr data register. ferr the ferr fag is the framing error fag. when this read only fag is 0 it indicates no framing error. when the flag is 1 it indicates that a framing error has been detected for the current character. the fag can also be cleared by a software sequence which will involve a read to the usr1 status register followed by an access to the rxr data register . nf the nf fag is the noise fag. when this read only fag is 0 it indicates a no noise condition. when the fag is 1 it indicates that the uart has detected noise on the receiver input. the nf fag is set during the same cycle as the rxif fag but will not be set in the case of an overrun. the nf fag can be cleared by a software sequence which will involve a read to the usr1 status register, followed by an access to the rxr data register.

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perr the perr fag is the parity error fag. when this read only fag is 0 it indicates that a parity error has not been detected. when the fag is 1 it indicates that the parity of the received word is incorrect. this error fag is applicable only if parity mode (odd or even) is selected. the fag can also be cleared by a software sequence which involves a read to the usr1 status register, followed by an access to the rxr data register.
rev 1.00 88 ???i? 1?? ? 011 rev 1.00 89 ???i? 1?? ? 011 HT82A824R usb audio mcu ucr1 register the usr1 register is the status register for the uart, which can be read by the program to determine the present status of the uart. all fags within the usr1 register are read only. further explanation on each of the fags is given below: tx8 this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data, known as tx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format. rx8 this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data, known as rx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format. txbrk the txbrk bit is the transmit break character bit. when this bit is 0 there are no break characters and the tx pin operates normally. when the bit is 1 there are transmit break characters and the transmitter will send logic zeros. when equal to 1 after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the txbrk bit is reset. stops this bit determines if one or two stop bits are to be used. when this bit is equal to 1 two stop bits are used, if the bit is equal to 0 then only one stop bit is used. prt this is the parity type selection bit. when this bit is equal to 1 odd parity will be selected, if the bit is equal to 0 then even parity will be selected. pren this is parity enable bit. when this bit is equal to 1 the parity function will be enabled, if the bit is equal to 0 then the parity function will be disabled. bno this bit is used to select the data length format, which can have a choice of either 8-bits or 9-bits. if this bit is equal to 1 then a 9-bit data length will be selected, if the bit is equal to 0 then an 8-bit data length will be selected. if 9-bit data length is selected then bits rx8 and tx8 will be used to store the 9th bit of the received and transmitted data respectively . uarten the uarten bit is the uart enable bit. when the bit is 0 the uart will be disabled and the rx and tx pins will function as general purpose i/o pins. when the bit is 1 the uart will be enabled and the tx and rx pins will function as defned by the txen and rxen control bits. when the uart is disabled it will empty the buffer so any character remaining in the buffer will be discarded. in addition, the baud rate counter value will be reset. when the uart is disabled, all error and status fags will be reset. the txen, rxen, txbrk, rxif, oerr, ferr, perr, and nf bits will be cleared, while the tidle, txif and ridle bits will be set. other control bits in ucr1, ucr2, and brg registers will remain unaffected. if the uart is active and the uarten bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defned above. when the uart is re-enabled it will restart in the same confguration.
rev 1.00 90 ???i? 1?? ? 011 rev 1.00 91 ???i? 1?? ? 011 HT82A824R usb audio mcu

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ucr2 register the ucr2 register is the second of the two uart control registers and serves several purposes. one of its main functions is to control the basic enable/disable operation of the uart transmitter and receiver as well as enabling the various uart interrupt sources. the register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. further explanation on each of the bits is given below: teie this bit enables or disables the transmitter empty interrupt. if this bit is equal to 1 when the transmitter empty txif flag is set, due to a transmitter empty condition, the uart interrupt request flag will be set. if this bit is equal to 0 the uart interrupt request flag will not be influenced by the condition of the txif flag. tiie this bit enables or disables the transmitter idle interrupt. if this bit is equal to 1 when the transmitter idle tidle flag is set, the uart interrupt request flag will be set. if this bit is equal to 0 the uart interrupt request flag will not be influenced by the condition of the tidle flag. rie this bit enables or disables the receiver interrupt. if this bit is equal to 1 when the receiver overrun oerr flag or receive data available rxif flag is set, the uart interrupt request flag will be set. if this bit is equal to 0 the uart interrupt will not be influenced by the condition of the oerr or rxif flags. wake this bit enables or disables the receiver wake-up function. if this bit is equal to 1 and if the mcu is in the power down mode, a low going edge on the rx input pin will wake-up the device. if this bit is equal to 0 and if the mcu is in the power down mode, any edge transitions on the rx pin will not wake-up the device.
rev 1.00 90 ???i? 1?? ? 011 rev 1.00 91 ???i? 1?? ? 011 HT82A824R usb audio mcu adden the adden bit is the address detect mode bit. when this bit is 1 the address detect mode is enabled. when this occurs, if the 8th bit, which corresponds to rx7 if bno=0, or the 9th bit, which corresponds to rx8 if bno=1, has a value of 1 then the received word will be identified as an address, rather than data. if the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8 or 9 bit depending on the value of bno. if the address bit is 0 an interrupt will not be generated, and the received data will be discarded. brgh the brgh bit selects the high or low speed mode of the baud rate generator. this bit, together with the value placed in the brg register, controls the baud rate of the uart. if this bit is equal to 1 the high speed mode is selected. if the bit is equal to 0 the low speed mode is selected. rxen the rxen bit is the receiver enable bit. when this bit is equal to 0 the receiver will be disabled with any pending data receptions being aborted. in addition the buffer will be reset. in this situation the rx pin can be used as a general purpose i/o pin. if the rxen bit is equal to 1 the receiver will be enabled and if the uarten bit is equal to 1 the rx pin will be controlled by the uart. clearing the rxen bit during a transmission will cause the data reception to be aborted and will reset the receiver. if this occurs, the rx pin can be used as a general purpose i/o pin.

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? ?? txen the txen bit is the transmitter enable bit. when this bit is equal to 0 the transmitter will be disabled with any pending transmissions being aborted. in addition the buffer will be reset. in this situation the tx pin can be used as a general purpose i/o pin. if the txen bit is equal to 1 the transmitter will be enabled and if the uarten bit is equal to 1 the tx pin will be controlled by the uart. clearing the txen bit during a transmission will cause the transmission to be aborted and will reset the transmitter. if this occurs, the tx pin can be used as a general purpose i/o pin.
rev 1.00 9? ???i? 1?? ? 011 rev 1.00 93 ???i? 1?? ? 011 HT82A824R usb audio mcu baud rate generator to setup the speed of the serial data communication, the uart function contains its own dedicated baud rate generator. the baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. the first of these is the value placed in the brg register and the second is the value of the brgh bit within the ucr2 control register. the brgh bit decides, if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. the value in the brg register determines the division factor, n, which is used in the following baud rate calculation formula. note that n is the decimal value placed in the brg register and has a range of between 0 and 255. ucr? brgh bit 0 1 baud rate f sys / (6?(n+1) f sys / (16(n+1) by programming the brgh bit which allows selection of the related formula and programming the required value in the brg register, the required baud rate can be setup. note that because the actual baud rate is determined using a discrete value, n, placed in the brg register, there will be an error associated between the actual and requested value. the following example shows how the brg register value n and the error value can be calculated. calculating the register and error values for a system frequency of 12mhz, and with brgh set to 0 determine the brg register value n, the actual baud rate and the error value for a desired baud rate of 4800. from the above table the desired baud rate br= f sys / (64(n+1) re-arranging this equation gives n = f sys /(br64)-1 giving a value for n= 12000000/(480064)-1=38.0625 to obtain the closest value, a decimal value of 38 should be placed into the brg register. this gives an actual or calculated baud rate value of br= 12000000/ (64(38+1) =4808 therefore the error is equal to (4808-4800)/4800= 0.16% the following tables show actual values of baud rate and error values for the two values of brgh. baud rate k/bps baud rates for brgh=0 f sys =12mhz f sys =6mhz brg kbaud error (%) brg kbaud error (%) 0.3 1.? 155 1.?0? 0.16 77 1.?0? 0.16 ?.? 77 ?.?0? 0.16 38 ?.?0? 0.16 ?.8 38 ?.808 0.16 19 ?.6875 -?.3? 9.6 19 9.375 -?.3? 9 9.375 -?.3? 19.? 9 18.75 -?.3? ? 18.75 -?.3? 38.? ? 37.5 -?.3? ? 31.?5 -18.6? 57.6 ? 6?.5 8.51 115. ? baud rates and error values for brgh=0
rev 1.00 9? ???i? 1?? ? 011 rev 1.00 93 ???i? 1?? ? 011 HT82A824R usb audio mcu baud rate k/bps baud rates for brgh=1 f sys =12mhz f sys =6mhz brg kbaud error (%) brg kbaud error (%) 0.3 1.? ?.? 155 ?.?0? 0.16 ?.8 155 ?.808 0.16 77 ?.808 0.16 9.6 77 9.615 0.16 38 9.615 0.16 19.? 38 19.?30 0.16 19 19.?30 0.16 38.? 19 37.500 -?.3? 9 37.500 -?.3? 57.6 1? 57.69? 0.16 6 53.57 -6.99 115. ? 6 107.143 -6.99 2 125.0 8.51 baud rates and error values for brgh=1 setting up and controlling the uart introduction for data transfer, the uart function utilizes a non-return-to-zero, more commonly known as nrz, format. this is composed of one start bit, eight or nine data bits, and one or two stop bits. parity is supported by the uart hardware, and can be setup to be even, odd or no parity. for the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, n, 1, is used as the default setting, which is the setting at power-on. the number of data bits and stop bits, along with the parity, are setup by programming the corresponding bno, prt, pren, and stops bits in the ucr1 register. the baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received lsb first. although the uarts transmitter and receiver are functionally independent, they both use the same data format and baud rate. in all cases stop bits will be used for data transmission. enabling/disabling the uart the basic on/off function of the internal uart function is controlled using the uarten bit in the ucr1 register. as the uart transmit and receive pins, tx and rx respectively, are pin-shared with normal i/o pins, one of the basic functions of the uarten control bit is to control the uart function of these two pins. if the uarten, txen and rxen bits are set, then these two i/o pins will be setup as a tx output pin and an rx input pin respectively, in effect disabling the normal i/o pin function. if no data is being transmitted on the tx pin then it will default to a logic high value. clearing the uarten bit will disable the tx and rx pins and allow these two pins to be used as normal i/o pins. when the uart function is disabled the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. disabling the uart will also reset the error and status flags with bits txen, rxen, txbrk, rxif, oerr, ferr, perr and nf being cleared while bits tidle, txif and ridle will be set. the remaining control bits in the ucr1, ucr2 and brg registers will remain unaffected. if the uarten bit in the ucr1 register is cleared while the uart is active, then all pending transmissions and receptions will be immediately suspended and the uart will be reset to a condition as defined above. if the uart is then subsequently re-enabled, it will restart again in the same configuration.
rev 1.00 9? ???i? 1?? ? 011 rev 1.00 95 ???i? 1?? ? 011 HT82A824R usb audio mcu data, parity and stop bit selection the format of the data to be transferred, is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. these factors are determined by the setup of various bits within the ucr1 register. the bno bit controls the number of data bits which can be set to either 8 or 9, the prt bit controls the choice of odd or even parity, the pren bit controls the parity on/off function and the stops bit decides whether one or two stop bits are to be used. the following table shows various formats for data transmission. the address bit identifies the frame as an address character. the number of stop bits, which can be either one or two, is independent of the data length. start bit data bits address bits parity bits stop bit example of 8-bit data formats 1 8 0 0 1 1 7 0 1 1 1 7 1 1 0 1 example of 8-bit data formats 1 9 0 0 1 1 8 0 1 1 1 8 1 1 0 1 the following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. uart transmitter data word lengths of either 8 or 9 bits, can be selected by programming the bno bit in the ucr1 register. when bno bit is set, the word length will be set to 9 bits. in this case the 9th bit, which is the msb, needs to be stored in the tx8 bit in the ucr1 register. at the transmitter core lies the transmitter shift register, more commonly known as the tsr, whose data is obtained from the transmit data register, which is known as the txr register. the data to be transmitted is loaded into this txr register by the application program. the tsr register is not written to with new data until the stop bit from the previous transmission has been sent out. as soon as this stop bit has been transmitted, the tsr can then be loaded with new data from the txr register, if it is available. it should be noted that the tsr register, unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. an actual transmission of data will normally be enabled when the txen bit is set, but the data will not be transmitted until the txr register has been loaded with data and the baud rate generator has defined a shift clock source. however, the transmission can also be initiated by first loading data into the txr register, after which the txen bit can be set. when a transmission of data begins, the tsr is normally empty, in which case a transfer to the txr register will result in an immediate transfer to the tsr. if during a transmission the txen bit is cleared, the transmission will immediately cease and the transmitter will be reset. the tx output pin will then return to having a normal general purpose i/o pin function. transmitting data when the uart is transmitting data, the data is shifted on the tx pin from the shift register, with the least significant bit first. in the transmit mode, the txr register forms a buffer between the internal bus and the transmitter shift register. it should be noted that if 9-bit data format has been selected, then the msb will be taken from the tx8 bit in the ucr1 register. the steps to initiate a data transfer can be summarized as follows:
rev 1.00 9? ???i? 1?? ? 011 rev 1.00 95 ???i? 1?? ? 011 HT82A824R usb audio mcu make the correct selection of the bno, prt, pren and stops bits to defne the required word length, parity type and number of stop bits. setup the brg register to select the desired baud rate. set the txen bit to ensure that the tx pin is used as a uart transmitter pin and not as an i/o pin. access the usr1 register and write the data that is to be transmitted into the txr register. note that this step will clear the txif bit. this sequence of events can now be repeated to send additional data. it should be noted that when txif=0, data will be inhibited from being written to the txr register. clearing the txif flag is always achieved using the following software sequence: 1. a usr1 register access 2. a txr register write execution the read-only txif flag is set by the uart hardware and if set indicates that the txr register is empty and that other data can now be written into the txr register without overwriting the previous data. if the teie bit is set then the txif flag will generate an interrupt. during a data transmission, a write instruction to the txr register will place the data into the txr register, which will be copied to the shift register at the end of the present transmission. when there is no data transmission in progress, a write instruction to the txr register will place the data directly into the shift register, resulting in the commencement of data transmission, and the txif bit being immediately set. when a frame transmission is complete, which happens after stop bits are sent or after the break frame, the tidle bit will be set. to clear the tidle bit the following software sequence is used: 1. a usr1 register access 2. a txr register write execution note: that both the txif and tidle bits are cleared by the same software sequence.

transmit break if the txbrk bit is set then break characters will be sent on the next transmission. break character transmission consists of a start bit, followed by 13n 0 bits and stop bits, where n=1, 2, etc. if a break character is to be transmitted then the txbrk bit must be first set by the application program, then cleared to generate the stop bits. transmitting a break character will not generate a transmit interrupt. note that a break condition length is at least 13 bits long. if the txbrk bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. after the application program has cleared the txbrk bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. the automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized.
rev 1.00 96 ???i? 1?? ? 011 rev 1.00 97 ???i? 1?? ? 011 HT82A824R usb audio mcu uart receiver introduction the uart is capable of receiving word lengths of either 8 or 9 bits. if the bno bit is set, the word length will be set to 9 bits with the msb being stored in the rx8 bit of the ucr1 register. at the receiver core lies the receive serial shift register, commonly known as the rsr. the data which is received on the rx external input pin is sent to the data recovery block. the data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. after the rx pin is sampled for the stop bit, the received data in rsr is transferred to the receive data register, if the register is empty. the data which is received on the external rx input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the rx pin. it should be noted that the rsr register, unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. receiving data when the uart receiver is receiving data, the data is serially shifted in on the external rx input pin, lsb first. in the read mode, the rxr register forms a buffer between the internal bus and the receiver shift register. the rxr register is a two byte deep fifo data buffer, where two bytes can be held in the fifo while a third byte can continue to be received. note that the application program must ensure that the data is read from rxr before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error oerr will be subsequently indicated. the steps to initiate a data transfer can be summarized as follows: make the correct selection of bno, prt, pren and stops bits to defne the word length, parity type and number of stop bits. setup the brg register to select the desired baud rate. set the rxen bit to ensure that the rx pin is used as a uart receiver pin and not as an i/o pin. at this point the receiver will be enabled which will begin to look for a start bit. when a character is received the following sequence of events will occur: the rxif bit in the usr1 register will be set when rxr register has data available, at least one more character can be read. when the contents of the shift register have been transferred to the rxr register, then if the rie bit is set, an interrupt will be generated. if during reception, a frame error, noise error, parity error, or an overrun error has been detected, then the error fags can be set. the rxif bit can be cleared using the following software sequence: 1. a usr1 register access 2. an rxr register read execution
rev 1.00 96 ???i? 1?? ? 011 rev 1.00 97 ???i? 1?? ? 011 HT82A824R usb audio mcu receive break any break character received by the uart will be managed as a framing error. the receiver will count and expect a certain number of bit times as specified by the values programmed into the bno and stops bits. if the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by bno and stops. the rxif bit is set, ferr is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the ridle bit is set. if a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the ferr flag, the receiver must wait for a valid stop bit before looking for the next start bit. the receiver will not make the assumption that the break condition on the line is the next start bit. a break is regarded as a character that contains only zeros with the ferr flag set. the break character will be loaded into the buffer and no further data will be received until stop bits are received. it should be noted that the ridle read only flag will go high when the stop bits have not yet been received. the reception of a break character on the uart registers will result in the following: the framing error fag, ferr, will be set. the receive data register, rxr, will be cleared. the oerr, nf, perr, ridle or rxif fags will possibly be set. idle status when the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the usr1 register, otherwise known as the ridle flag, will have a zero value. in between the reception of a stop bit and the detection of the next start bit, the ridle flag will have a high value, which indicates the receiver is in an idle condition. receiver interrupt the read only receive interrupt flag rxif in the usr1 register is set by an edge generated by the receiver. an interrupt is generated if rie=1, when a word is transferred from the receive shift register, rsr, to the receive data register, rxr. an overrun error can also generate an interrupt if rie=1. managing receiver errors several types of reception errors can occur within the uart module, the following section describes the various types and how they are managed by the uart. . overrun error C oerr flag the rxr register is composed of a two byte deep fifo data buffer, where two bytes can be held in the fifo register, while a third byte can continue to be received. before this third byte has been entirely shifted in, the data should be read from the rxr register. if this is not done, the overrun error flag oerr will be consequently indicated. in the event of an overrun error occurring, the following will happen: the oerr fag in the usr1 register will be set. the rxr contents will not be lost. the shift register will be overwritten. an interrupt will be generated if the rie bit is set. the oerr flag can be cleared by an access to the usr1 register followed by a read to the rxr register.
rev 1.00 98 ???i? 1?? ? 011 rev 1.00 99 ???i? 1?? ? 011 HT82A824R usb audio mcu noise error C nf flag over-sampling is used for data recovery to identify valid incoming data and noise. if noise is detected within a frame the following will occur: the read only noise fag, nf, in the usr1 register will be set on the rising edge of the rxif bit. data will be transferred from the shift register to the rxr register . no interrupt will be generated. however this bit rises at the same time as the rxif bit which itself generates an interrupt. note that the nf flag is reset by a usr1 register read operation followed by an rxr register read operation. framing error C ferr flag the read only framing error flag, ferr, in the usr1 register, is set if a zero is detected instead of stop bits. if two stop bits are selected, both stop bits must be high, otherwise the ferr flag will be set. the ferr flag is buffered along with the received data and is cleared on any reset. parity error C perr flag the read only parity error flag, perr, in the usr1 register, is set if the parity of the received word is incorrect. this error flag is only applicable if the parity is enabled, pren = 1, and if the parity type, odd or even is selected. the read only perr flag is buffered along with the received data bytes. it is cleared on any reset. it should be noted that the ferr and perr flags are buffered along with the corresponding word and should be read before reading the data word. uart interrupt scheme the uart internal function possesses its own internal interrupt and independent interrupt vector. several individual uart conditions can generate an internal uart interrupt. these conditions are, a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an rx pin wake-up. when any of these conditions are created, if the uart interrupt is enabled and the stack is not full, the program will jump to the uart interrupt vector where it can be serviced before returning to the main program. four of these conditions, have a corresponding usr1 register flag, which will generate a uart interrupt if its associated interrupt enable flag in the ucr2 register is set. the two transmitter interrupt conditions have their own corresponding enable bits, while the two receiver interrupt conditions have a shared enable bit. these enable bits can be used to mask out individual uart interrupt sources. the address detect condition, which is also a uart interrupt source, does not have an associated flag, but will generate a uart interrupt when an address detect condition occurs if its function is enabled by setting the adden bit in the ucr2 register. an rx pin wake-up, which is also a uart interrupt source, does not have an associated flag, but will generate a uart interrupt if the microcontroller is woken up by a low going edge on the rx pin, if the wake and rie bits in the ucr2 register are set. note that in the event of an rx wake-up interrupt occurring, there will be a delay of 1024 system clock cycles before the system resumes normal operation. note that the usr1 register flags are read only and cannot be cleared or set by the application program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the case for some of the other interrupts. the flags will be cleared automatically when certain actions are taken by the uart, the details of which are given in the uart register section. the overall uart interrupt can be disabled or enabled by the euri bit in the mfi1c interrupt control register to prevent a uart interrupt from occurring.
rev 1.00 98 ???i? 1?? ? 011 rev 1.00 99 ???i? 1?? ? 011 HT82A824R usb audio mcu
? ? ?? ? ? ? ?? ? ? ? ? ? - ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? uart interrupt scheme address detect mode setting the address detect mode bit, adden, in the ucr2 register, enables this special mode. if this bit is enabled then an additional qualifier will be placed on the generation of a receiver data available interrupt, which is requested by the rxif flag. if the adden bit is enabled, then when data is available, an interrupt will only be generated, if the highest received bit has a high value. note that the euri and emi interrupt enable bits must also be enabled for correct interrupt generation. this highest address bit is the 9th bit if bno=1 or the 8th bit if bno=0. if this bit is high, then the received word will be defined as an address rather than data. a data available interrupt will be generated every time the last bit of the received word is set. if the adden bit is not enabled, then a receiver data available interrupt will be generated each time the rxif flag is set, irrespective of the data last bit status. the address detect mode and parity enable are mutually exclusive functions. therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity enable bit to zero. adden bit 9 if bno = 1, bit 8 if bno = 0 uart interrupt generated 0 0 1 1 0 1
rev 1.00 100 ???i? 1?? ? 011 rev 1.00 101 ???i? 1?? ? 011 HT82A824R usb audio mcu uart operation in power down mode when the mcu is in the power down mode the uart will cease to function. when the device enters the power down mode, all clock sources to the module are shutdown. if the mcu enters the power down mode while a transmission is still in progress, then the transmission will be terminated and the external tx transmit pin will be forced to a logic high level. in a similar way, if the mcu enters the power down mode while receiving data, then the reception of data will likewise be terminated. when the mcu enters the power down mode, note that the usr1, ucr1, ucr2, transmit and receive registers, as well as the brg register will not be af fected. the uart function contains a receiver rx pin wake-up function, which is enabled or disabled by the wake bit in the ucr2 register. if this bit, along with the uart enable bit, uarten, the receiver enable bit, rxen and the receiver interrupt bit, rie, are all set before the mcu enters the power down mode, then a falling edge on the rx pin will wake-up the mcu from the power down mode. note that as it takes 1024 system clock cycles after a wake-up, before normal microcontroller operation resumes, any data received during this time on the rx pin will be ignored. for a uart wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global interrupt enable bit, emi, and the uart interrupt enable bit, euri must also be set. if these two bits are not set then only a wake up event will occur and no interrupt will be generated. note also that as it takes 1024 system clock cycles after a wake-up before normal microcontroller resumes, the uart interrupt will not be generated until after this time has elapsed. pulse width modulator the device contains a 2 channel pulse width modulator function, more commonly known as pwm. useful for such applications such as motor speed control, the pwm function provides outputs with a fxed frequency but with a duty cycle that can be varied by setting particular values into the corresponding pwm registers. the device has two pwm outputs for which two 8-bit pwm registers are provided and are known as pwm0 and pwm1. it is in these registers, that the 8-bit value, which represents the overall duty cycle of one modulation cycle of the output waveform, should be placed. to increase the pwm modulation frequency, each modulation cycle is modulated into two or four individual modulation sub-sections, known as the 7+1 mode or 6+2 respectively. the mode selection is made using the pwmc register. note that it is only necessary to write the required modulation value into the corresponding pwm0 or pwm1 register, as the subdivision of the waveform into its sub-modulation cycles is implemented automatically within the microcontroller hardware. for all devices, the pwm clock source is the system clock f sys . this method of dividing the original modulation cycle into a further 2 or 4 sub-cycles enables the generation of higher pwm frequencies, which allow a wider range of applications to be served. as long as the periods of the generated pwm pulses are less than the time constants of the load, the pwm output will be suitable for driving, as such long time constant loads will average out the pulses of the pwm output. the difference between what is known as the pwm cycle frequency and the pwm modulation frequency should be understood. as the pwm clock is the system clock, f sys , and as the pwm value is 8-bits wide, the overall pwm cycle frequency is f sys /256. however when in the 7+1 mode of operation, the pwm modulation frequency will be f sys /128, while the pwm modulation frequency for the 6+2 mode of operation will be f sys /64. the overall pwm output enable/disable is controlled using the pwmc register which acts like an on/off switch for each pwm output.
rev 1.00 100 ???i? 1?? ? 011 rev 1.00 101 ???i? 1?? ? 011 HT82A824R usb audio mcu pwm modulation frequency pwm cycle frequency pwm cycle duty f sys /6? fo? (6+?) bits mode f sys /1?8 fo? (7+1) bits mode f sys /?56 [pwm]/?56 6+2 pwm mode each full pwm cycle, as it is controlled by an 8-bit pwm0 or pwm1 register, has 256 clock periods. however, in the 6+2 pwm mode, each pwm cycle is subdivided into four individual sub- cycles known as modulation cycle 0~modulation cycle 3, denoted as i in the table. each one of these four sub-cycles contains 64 clock cycles. in this mode, a modulation frequency increase by a factor of four is achieved. the 8-bit pwm0 or pwm1 register value, which represents the overall duty cycle of the pwm waveform, is divided into two groups. the frst group which consists of bit2~bit7 is denoted here as the dc value. the second group which consists of bit0~bit1 is known as the ac value. in the 6+2 pwm mode, the duty cycle value of each of the four modulation sub- cycles is shown in the following table. parameter ac (0~3) dc (duty cycle) modu?ation cyc?e i (i=0~3) i < ?c dc+1 6? i ac dc 6? 6+2 mode modulation cycle values the following diagram illustrates the waveforms associated with the 6+2 mode of pwm operation. it is important to note how the single pwm cycle is subdivided into 4 individual modulation cycles, numbered from 0~3 and how the ac value is related to the pwm value.

?
(6+2) pwm mode output waveform pulse width modulation registers for (6+2) pwm mode
rev 1.00 10? ???i? 1?? ? 011 rev 1.00 103 ???i? 1?? ? 011 HT82A824R usb audio mcu 7+1 pwm mode each full pwm cycle, as it is controlled by an 8-bit pwm0 or pwm1 register, has 256 clock periods. however, in the 7+1 pwm mode, each pwm cycle is subdivided into two individual sub- cycles known as modulation cycle 0~modulation cycle 1, denoted as i in the table. each one of these two sub-cycles contains 128 clock cycles. in this mode, a modulation frequency increase by a factor of two is achieved. the 8-bit pwm0 or pwm1 register value, which represents the overall duty cycle of the pwm waveform, is divided into two groups. the frst group which consists of bit1~bit7 is denoted here as the dc value. the second group which consists of bit0 is known as the ac value. in the 7+1 pwm mode, the duty cycle value of each of the two modulation sub-cycles is shown in the following table. parameter ac (0~3) dc (duty cycle) modu?ation cyc?e i (i=0~1) i < ?c dc+1 1?8 i ac dc 1?8 7+1 mode modulation cycle values the following diagram illustrates the waveforms associated with the 7+1 mode of pwm operation. it is important to note how the single pwm cycle is subdivided into 2 individual modulation cycles, numbered from 0~1 and how the ac value is related to the pwm value in the 7+1 pwm mode.
? (7+1) pwm mode output waveform pulse width modulation registers for (7+1) pwm mode
rev 1.00 10? ???i? 1?? ? 011 rev 1.00 103 ???i? 1?? ? 011 HT82A824R usb audio mcu pwm output control control of the two pwm outputs is achieved using the pwmc register. bits within this register control the on/off function of the individual pwm outputs as well as their chosen mode type. note than when the pwm outputs are disabled they will remain in a low state.

? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? - ? - ? - ? - ? pwm control register - pwmc pwm programming example the following sample program shows how the pwm outputs are setup and controlled. before use the corresponding pwm output confguration options must frst be selected. mov a,64h ; setup pwm0 value of 100 decimal which is 64h mov pwm0,a clr pwmc.pwm_mod0 ; setup pin pwm0 to the 6+2 pwm mode set pwmc.pwm_en0 ; enable pwm0 output : : : : clr pwmc.pwm_en0 ; disable pwm0 output
rev 1.00 10? ???i? 1?? ? 011 rev 1.00 105 ???i? 1?? ? 011 HT82A824R usb audio mcu confguration options confguration options refer to certain options within the mcu that are programmed into the otp program memory device during the programming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later by the application software. all options must be defned for proper system function, the details of which are shown in the table. no. options i/o options 1 p ?0~p ?7: ?u??-high enab?e o? disab?e (bit o?tion) ? pb0~pb?: ?u??-high enab?e o? disab?e (bit o?tion) 3 pc0~pc7: ?u??-high enab?e o? disab?e (nibb?e o?tion) ? p ?0~p ?7: wake u? enab?e o? disab?e (bit o?tion) 5 pb0~pb?: wake u? enab?e o? disab?e (bit o?tion) 6 pc0~pc7: wake u? enab?e o? disab?e (nibb?e o?tion) 7 p ?0~p ?7: cmos o? nmos out?ut ty?e (bit o?tion) watchdog options 8 wdt: enab ?e o? disab?e 9 clrwdt inst ?uctions: one o? two inst?uctions 10 wdt c ?ock sou?ce: f sys /? o? wdt osci??ato? lvr option 11 lvr function: enab ?e o? disab?e tbhp option 1? tbhp enab ?e o? disab?e io vdd option 13 vdd o? v33o fo? p ??~p ?7 (nibb?e o?tion) 1? vdd o? v33o fo? pb0~pb? (bit o?tion) 15 vdd o? v33o fo? pc?~pc7 (nibb?e o?tion)
rev 1.00 10? ???i? 1?? ? 011 rev 1.00 105 ???i? 1?? ? 011 HT82A824R usb audio mcu application circuits p?1 p?? d+ d- p?3 p?0 vdd vdd music_in_l music_in_r ? n0 ? n1 usbdn dvdd vss lout rout vdd dvdd ? vdd ? vref_l bi ?s v33o ?vss1 vss dvdd ?vss1 resetb vref_r usbdp usbdn osco ? n1 pc6 ?vss1 pb1 pb? vref_l ?n ? pc1 lout ? vdd3 p?0 ? vdd ? ?n ? pb3 p?3 p?1 v33o pc0 p?6 bi ?s pc ? pb0 pc7 pc3 p?7 pc ? rout pc5 p?5 p?? p?? music_r ? n3 ?vss3 ? vdd1 dvss1 music_l vref_r ?vss1 pb? ? n0 usbdp ? n5 osci music_in_r music_r music_in_l music_l ?vss1 sw ? p?? sw5 p?3 1 ? + c ? 9 1uf c51 0.1uf c56 0.1uf c9 0.1uf c36 0.1uf c7 ? 7 ? c8 ? 7 ? l5 be ? d ferrite 1 ? c19 0.1uf c53 0.1uf c5 ? 0.1uf r1 ? 330 r6 1.5k sw3 p?1 u1 ht8 ?? 8 ?? r lqfp- ?8 9 8 6 ? 5 7 ? ? 8 1 3 11 10 ? 7 ? 6 ? 5 ?? ? 3 ?? ? 1 ? 0 39 38 36 35 3 ? 33 3 ? 31 30 ? 9 ? 8 ? 7 ? 6 ? 3 ?? ? 1 ? 0 19 18 17 16 15 1 ? 13 1 ? ?? 37 ? 5 rout lout bi ?s music_in_r music_in_l ?vss? ?vss1 vref_r vref_l ? vdd1 ? vdd3 ? vdd ? p?0 p?1 p?? p?3 mclk/p ?? sclk/p ?5 lrck/p ?6 sd ?t ? /p?7 dvss1 v33o usbdn dvdd1 resetb osco osci pc0/bz pc1/tmr0 pc ? /tmr1 pc3/intb pc ? /sdo pc5/sdi pb0/tx pb1/rx pb? /pwm0 pb3/pwm1 pb? ?vss3 ? n0 ? n1 ?n ? ? n3 ?n ? ? n5 pc7/sck usbdp pc6/scsb y1 1 ? mhz r? 100k c6 0.1uf l ? be ? d ferrite 1 ? + c? 1uf c ? 0 1uf sw1 reset c3 0.1uf + c5 ? 10uf l9 be ? d ferrite 1 ? l10 be ? d ferrite 1 ? + c35 1uf + c1 ? 100uf + c11 100uf + c ? 8 1uf j5 ? udio out stereo 3 ? 1 c50 0.1uf c ? 6 0.1uf c ? 7 0.1uf j1 usb con 1 ? 3 ? vdd usb- usb+ vss r5 33 r? 33 d? gled l6 be?d 1 ? spk volume dec spk volume inc spk mute usb active avss1 avss1 avss1 avss1 avss1 avss1 avss1 avss1 ground plane connection
rev 1.00 106 ???i? 1?? ? 011 rev 1.00 107 ???i? 1?? ? 011 HT82A824R usb audio mcu instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5s and branch or call instructions would be implemented within 1s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different
rev 1.00 106 ???i? 1?? ? 011 rev 1.00 107 ???i? 1?? ? 011 HT82A824R usb audio mcu rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively. the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is normally implemented by using registers. however, when working with large amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "halt" instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev 1.00 108 ???i? 1?? ? 011 rev 1.00 109 ???i? 1?? ? 011 HT82A824R usb audio mcu instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic ?dd ??[m] ?dd data memo?y to ?cc 1 z? c? ?c? ov ?ddm ??[m] ?dd ?cc to data memo?y 1 note z? c? ?c? ov ?dd ??x ?dd immediate data to ?cc 1 z? c? ?c? ov ?dc ??[m] ?dd data memo?y to ?cc with ca??y 1 z? c? ?c? ov ?dcm ??[m] ?dd ?cc to data memo?y with ca??y 1 note z? c? ?c? ov sub ??x subt?act immediate data f?om the ?cc 1 z? c? ?c? ov sub ??[m] subt?act data memo?y f?om ?cc 1 z? c? ?c? ov subm ??[m] subt?act data memo?y f?om ?cc with ?esu?t in data memo?y 1 note z? c? ?c? ov sbc ??[m] subt?act data memo?y f?om ?cc with ca??y 1 z? c? ?c? ov sbcm ??[m] subt?act data memo?y f?om ?cc with ca??y ? ?esu?t in data memo?y 1 note z? c? ?c? ov d?? [m] decima? adjust ?cc fo? ?ddition with ?esu?t in data memo?y 1 note c logic operation ?nd ??[m] logica? ?nd data memo?y to ?cc 1 z or ??[m] logica? or data memo?y to ?cc 1 z xor ??[m] logica? xor data memo?y to ?cc 1 z ?ndm ??[m] logica? ?nd ?cc to data memo?y 1 note z orm ??[m] logica? or ?cc to data memo?y 1 note z xorm ??[m] logica? xor ?cc to data memo?y 1 note z ?nd ??x logica? ?nd immediate data to ?cc 1 z or ??x logica? or immediate data to ?cc 1 z xor ??x logica? xor immediate data to ?cc 1 z cpl [m] com??ement data memo?y 1 note z cpl? [m] com??ement data memo?y with ?esu?t in ?cc 1 z increment & decrement inc? [m] inc?ement data memo?y with ?esu?t in ?cc 1 z inc [m] inc?ement data memo?y 1 note z dec? [m] dec?ement data memo?y with ?esu?t in ?cc 1 z dec [m] dec?ement data memo?y 1 note z rotate rr? [m] rotate data memo?y ?ight with ?esu?t in ?cc 1 none rr [m] rotate data memo?y ?ight 1 note none rrc? [m] rotate data memo?y ?ight th?ough ca??y with ?esu?t in ?cc 1 c rrc [m] rotate data memo?y ?ight th?ough ca??y 1 note c rl? [m] rotate data memo?y ?eft with ?esu?t in ?cc 1 none rl [m] rotate data memo?y ?eft 1 note none rlc? [m] rotate data memo?y ?eft th?ough ca??y with ?esu?t in ?cc 1 c rlc [m] rotate data memo?y ?eft th?ough ca??y 1 note c
rev 1.00 108 ???i? 1?? ? 011 rev 1.00 109 ???i? 1?? ? 011 HT82A824R usb audio mcu mnemonic description cycles flag affected data move mov ??[m] move data memo?y to ?cc 1 none mov [m]?? move ?cc to data memo?y 1 note none mov ??x move immediate data to ?cc 1 none bit operation clr [m].i c?ea? bit of data memo?y 1 note none set [m].i set bit of data memo?y 1 note none branch jmp add ? jum? unconditiona??y ? none sz [m] ski? if data memo?y is ze?o 1 note none sz? [m] ski? if data memo?y is ze?o with data movement to ?cc 1 note none sz [m].i ski? if bit i of data memo?y is ze?o 1 note none snz [m].i ski? if bit i of data memo?y is not ze?o 1 note none siz [m] ski? if inc?ement data memo?y is ze?o 1 note none sdz [m] ski? if dec?ement data memo?y is ze?o 1 note none siz? [m] ski? if inc?ement data memo?y is ze?o with ?esu?t in ?cc 1 note none sdz? [m] ski? if dec?ement data memo?y is ze?o with ?esu?t in ?cc 1 note none c? ll add? sub?outine ca?? ? none ret retu?n f?om sub?outine ? none ret ??x retu?n f?om sub?outine and ?oad immediate data to ?cc ? none reti retu?n f?om inte??u?t ? none table read t ?brdc [m] read tab?e (cu??ent ? age) to tblh and data memo?y ? note none t ? brdl [m] read tab?e (?ast ? age) to tblh and data memo?y ? note none miscellaneous nop no o?e?ation 1 none clr [m] c?ea? data memo?y 1 note none set [m] set data memo?y 1 note none clr wdt c?ea? watchdog time? 1 to ? pdf clr wdt1 p?e-c?ea? watchdog time? 1 to ? pdf clr wdt? p?e-c?ea? watchdog time? 1 to ? pdf sw ? p [m] swa? nibb?es of data memo?y 1 note none sw ?p ? [m] swa? nibb?es of data memo?y with ?esu?t in ?cc 1 none h? lt ente? ?owe? down mode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the "clr wdt1" and "clr wdt2" instructions the to and pdf fags may be affected by the execution status. the to and pdf fags are cleared after both "clr wdt1" and "clr wdt2" instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
rev 1.00 110 ???i? 1?? ? 011 rev 1.00 111 ???i? 1?? ? 011 HT82A824R usb audio mcu instruction defnition ?dd data memo?y to ?cc with ca??y the contents of the specifed data memory, accumulator and the carry fag are added. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc + [m] + c ov ? z? ?c? c ?dd ?cc to data memo?y with ca??y the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the specifed data memory. [m] ?cc + [m] + c ov ? z? ?c? c ?dd data memo?y to ?cc the contents of the specifed data memory and the accumulator are added. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc + [m] ov ? z? ?c? c ?dd immediate data to ?cc the contents of the accumulator and the specifed immediate data are added. the ?esu?t is sto?ed in the ?ccumu?ato? . ?c ?cc + x ov ? z? ?c? c ?dd ?cc to data memo?y the contents of the specifed data memory and the accumulator are added. the result is stored in the specifed data memory. [m] ?cc + [m] ov ? z? ?c? c logica? ?nd data memo?y to ?cc data in the accumulator and the specifed data memory perform a bitwise logical ?nd o?e? ation. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc " ?nd " [m] z logica? ?nd immediate data to ?cc data in the ?ccumu?ato? and the s?ecified immediate data ?e?fo? m a bitwise ?ogica? ?nd o?e? ation. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc " ?nd " x z logica? ?nd ?cc to data memo?y data in the specifed data memory and the accumulator perform a bitwise logical ?nd o?e? ation. the ?esu?t is sto?ed in the data memo? y. [m] ?cc " ?nd " [m] z adc a,[m] desc?i?tion o?e?ation affected fag(s) adcm a,[m] desc?i?tion o?e?ation affected fag(s) add a,[m] desc?i?tion o?e?ation affected fag(s) add a,x desc?i?tion o?e?ation affected fag(s) addm a,[m] desc?i?tion o?e?ation affected fag(s) and a,[m] desc?i?tion o?e?ation affected fag(s) and a,x desc?i?tion o?e?ation affected fag(s) andm a,[m] desc?i?tion o?e?ation affected fag(s)
rev 1.00 110 ???i? 1?? ? 011 rev 1.00 111 ???i? 1?? ? 011 HT82A824R usb audio mcu sub?outine ca?? unconditionally calls a subroutine at the specifed address. the program counter then inc ? ements by 1 to obtain the add? ess of the next inst ? uction which is then ? ushed onto the stack. the s?ecified add?ess is then ?oaded and the ??og? am continues execution f ? om this new add ? ess. ? s this inst? uction ? equi ? es an additiona? o?e?ation? it is a two cyc?e inst?uction. stack p?og?am counte? + 1 p?og?am counte? add? none c?ea? data memo?y each bit of the specifed data memory is cleared to 0. [m] 00h none c?ea? bit of data memo?y bit i of the specifed data memory is cleared to 0. [m].i 0 none c?ea? watchdog time? the to, pdf fags and the wdt are all cleared. wdt c ?ea?ed to 0 pdf 0 to ? pdf p?e-c?ea? watchdog time? the to, pdf fags and the wdtare all cleared. note that this instruction works in conjunction with clr wdt ? and must be executed a?te?nate? y with clr wdt? to have effect. re ?etitive? y executing this inst? uction without a?te?nate? y executing clr wdt? wi?? have no effect. wdt c ?ea?ed to 0 pdf 0 to ? pdf p?e-c?ea? watchdog time? the to, pdf fags and the wdtare all cleared. note that this instruction works in conjunction with clr wdt1 and must be executed a ?te?nate? y with clr wdt1 to have effect. re ?etitive? y executing this inst? uction without a?te?nate? y executing wdt c ?ea?ed to 0 pdf 0 to ? pdf call addr desc?i?tion o?e?ation affected fag(s) clr [m] desc?i?tion o?e?ation affected fag(s) clr [m].i desc?i?tion o?e?ation affected fag(s) clr wdt desc?i?tion o?e?ation affected fag(s) clr wdt1 desc?i?tion o?e?ation affected fag(s) clr wdt2 desc?i?tion o?e?ation affected fag(s)
rev 1.00 11 ? ???i? 1?? ? 011 rev 1.00 113 ???i? 1?? ? 011 HT82A824R usb audio mcu com??ement data memo?y each bit of the s ?ecified data memo? y is ?ogica??y com?? emented (1 ' s com ?? ement). bits which ?? evious ? y contained a 1 a? e changed to 0 and vice ve?sa. [m] [m] z com??ement data memo?y with ?esu?t in ?cc each bit of the s ?ecified data memo? y is ?ogica??y com?? emented (1 ' s com ?? ement). bits which ?? evious ? y contained a 1 a? e changed to 0 and vice ve? sa. the com??emented ?esu?t is sto?ed in the ?ccumu?ato? and the contents of the data memo?y ?emain unchanged. ?cc [m] z decima?-?djust ?cc fo? addition with ?esu?t in data memo?y conve?t the contents of the ?ccumu?ato? va?ue to a bcd ( bina? y coded decima?) va?ue ?esu? ting f?om the ?? evious addition of two bcd va?iab? es. if the ?ow nibb?e is greater than 9 or if ac fag is set, then a value of 6 will be added to the low nibb? e. othe? wise the ? ow nibb?e ? emains unchanged. if the high nibb? e is g?eate? than 9 or if the c fag is set, then a value of 6 will be added to the high nibble. essentia??y ? the decima? conve?sion is ?e?fo?med by adding 00h? 06h? 60h o? 66h depending on the accumulator and fag conditions. only the c fag may be affected by this inst ? uction which indicates that if the o?igina? bcd sum is g?eate? than 100? it a??ows mu?ti??e ??ecision decima? addition. [m] ?cc + 00h o? [m] ?cc + 06h o? [m] ?cc + 60h o? [m] ?cc + 66h c dec?ement data memo?y data in the specifed data memory is decremented by 1. [m] [m] C 1 z dec?ement data memo?y with ?esu?t in ?cc data in the specifed data memory is decremented by 1. the result is stored in the ?ccumu?ato? . the contents of the data memo ?y ?emain unchanged. ?cc [m] C 1 z cpl [m] desc?i?tion o?e?ation affected fag(s) cpla [m] desc?i?tion o?e?ation affected fag(s) daa [m] desc?i?tion o?e?ation affected fag(s) dec [m] desc?i?tion o?e?ation affected fag(s) deca [m] desc?i?tion o?e?ation affected fag(s)
rev 1.00 11 ? ???i? 1?? ? 011 rev 1.00 113 ???i? 1?? ? 011 HT82A824R usb audio mcu ente? ?owe? down mode this inst?uction sto?s the ??og?am execution and tu? ns off the system c? ock. the contents of the data memo ?y and ?egiste?s a?e ? etained. the wdt and ??esca?e? a? e c?ea? ed. the ?owe? down f? ag pdf is set and the wdt time-out f? ag to is c?ea?ed. to 0 pdf 0 to ? pdf inc?ement data memo?y data in the specifed data memory is incremented by 1. [m] [m]+1 z inc?ement data memo?y with ?esu?t in ?cc data in the specifed data memory is incremented by 1. the result is stored in the ?ccumu?ato? . the contents of the data memo ?y ?emain unchanged. ?cc [m]+1 z jum? unconditiona??y the contents of the p ?og? am counte? a?e ?e?? aced with the s? ecified add? ess. p? og ? am execution then continues f? om this new add ? ess. ? s this ? equi ? es the inse? tion of a dummy inst?uction whi?e the new add?ess is ?oaded? it is a two cyc?e inst?uction. p?og?am counte? add? none move data memo?y to ?cc the contents of the specifed data memory are copied to the accumulator. ?cc [m] none move immediate data to ?cc the immediate data specifed is loaded into the accumulator. ?cc x none move ?cc to data memo?y the contents of the accumulator are copied to the specifed data memory. [m] ?cc none no o?e?ation no o?e?ation is ?e?fo?med. execution continues with the next inst?uction. no o?e?ation none halt desc?i?tion o?e?ation affected fag(s) inc [m] desc?i?tion o?e?ation affected fag(s) inca [m] desc?i?tion o?e?ation affected fag(s) jmp addr desc?i?tion o?e?ation affected fag(s) mov a,[m] desc?i?tion o?e?ation affected fag(s) mov a,x desc?i?tion o?e?ation affected fag(s) mov [m],a desc?i?tion o?e?ation affected fag(s) nop desc?i?tion o?e?ation affected fag(s)
rev 1.00 11 ? ???i? 1?? ? 011 rev 1.00 115 ???i? 1?? ? 011 HT82A824R usb audio mcu logica? or data memo?y to ?cc data in the accumulator and the specifed data memory perform a bitwise logical or o?e? ation. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc " or " [m] z logica? or immediate data to ?cc data in the ?ccumu?ato? and the s?ecified immediate data ?e?fo? m a bitwise ?ogica? or o?e? ation. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc " or " x z logica? or ?cc to data memo?y data in the specifed data memory and the accumulator perform a bitwise logical or o?e? ation. the ?esu?t is sto?ed in the data memo? y. [m] ?cc " or " [m] z retu?n f?om sub?outine the p?og?am counte? is ?esto?ed f? om the stack. p?og?am execution continues at the ?esto?ed add?ess. p?og?am counte? stack none retu?n f?om sub?outine and ?oad immediate data to ?cc the p?og?am counte? is ?esto?ed f?om the stack and the ?ccumu?ato? ? oaded with the specifed immediate data. program execution continues at the restored add?ess. p?og?am counte? stack ?cc x none retu?n f?om inte??u?t the p?og?am counte? is ?esto?ed f? om the stack and the inte??u?ts a?e ?e-enab?ed by setting the emi bit. emi is the maste ? inte??u?t g?oba? enab? e bit. if an inte??u?t was ? ending when the reti inst? uction is executed? the ? ending inte??u?t ?outine wi?? be ??ocessed befo?e ?etu?ning to the main ??og?am. p?og?am counte? stack emi 1 none rotate data memo?y ?eft the contents of the s ? ecified data memo ?y a ? e ? otated ? eft by 1 bit with bit 7 ?otated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 none or a,[m] desc?i?tion o?e?ation affected fag(s) or a,x desc?i?tion o?e?ation affected fag(s) orm a,[m] desc?i?tion o?e?ation affected fag(s) ret desc?i?tion o?e?ation affected fag(s) ret a,x desc?i?tion o?e?ation affected fag(s) reti desc?i?tion o?e?ation affected fag(s) rl [m] desc?i?tion o?e?ation affected fag(s)
rev 1.00 11 ? ???i? 1?? ? 011 rev 1.00 115 ???i? 1?? ? 011 HT82A824R usb audio mcu rotate data memo?y ?eft with ?esu?t in ?cc the contents of the s ? ecified data memo ?y a ? e ? otated ? eft by 1 bit with bit 7 ? otated into bit 0. the ?otated ?esu?t is sto?ed in the ?ccumu?ato? and the contents of the data memo?y ?emain unchanged. ?cc.(i+1) [m].i; (i = 0~6) ?cc.0 [m].7 none rotate data memo?y ?eft th?ough ca??y the contents of the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 c rotate data memo?y ?eft th?ough ca??y with ?esu?t in ?cc data in the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into the bit 0. the ?otated ?esu? t is sto? ed in the ?ccumu?ato? and the contents of the data memo? y ?emain unchanged. ?cc.(i+1) [m].i; (i = 0~6) ?cc.0 c c [m].7 c rotate data memo?y ?ight the contents of the s?ecified data memo?y a?e ?otated ? ight by 1 bit with bit 0 ?otated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 none rotate data memo?y ?ight with ?esu?t in ?cc data in the s ? ecified data memo? y and the ca??y f ?ag a?e ? otated ? ight by 1 bit with bit 0 ? otated into bit 7. the ?otated ?esu? t is sto?ed in the ?ccumu?ato ? and the contents of the data memo?y ?emain unchanged. ?cc.i [m].(i+1); (i = 0~6) ?cc.7 [m].0 none rotate data memo?y ?ight th?ough ca??y the contents of the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 c rla [m] desc?i?tion o?e?ation affected fag(s) rlc [m] desc?i?tion o?e?ation affected fag(s) rlca [m] desc?i?tion o?e?ation affected fag(s) rr [m] desc?i?tion o?e?ation affected fag(s) rra [m] desc?i?tion o?e?ation affected fag(s) rrc [m] desc?i?tion o?e?ation affected fag(s)
rev 1.00 116 ???i? 1?? ? 011 rev 1.00 117 ???i? 1?? ? 011 HT82A824R usb audio mcu rotate data memo?y ?ight th?ough ca??y with ?esu?t in ?cc data in the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. the rotated ?esu?t is sto?ed in the ?ccumu?ato? and the contents of the data memo?y ? emain unchanged. ?cc.i [m].(i+1); (i = 0~6) ?cc.7 c c [m].0 c subt?act data memo?y f?om ?cc with ca??y the contents of the specifed data memory and the complement of the carry fag a?e subt?acted f? om the ?ccumu?ato? . the ?esu?t is sto?ed in the ?ccumu?ato? . note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. ?cc ?cc C [m] C c ov ? z? ?c? c subt?act data memo?y f?om ?cc with ca??y and ?esu?t in data memo?y the contents of the specifed data memory and the complement of the carry fag a?e subt? acted f? om the ?ccumu?ato? . the ?esu? t is sto? ed in the data memo? y. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. ?cc ?cc C [m] C c ov ? z? ?c? c ski? if dec?ement data memo?y is 0 the contents of the specifed data memory are frst decremented by 1. if the result is 0 the fo?? owing inst? uction is ski??ed. ?s this ?equi? es the inse? tion of a dummy inst?uction whi?e the next inst?uction is fetched? it is a two cyc?e inst? uction. if the ?esu?t is not 0 the ??og?am ??oceeds with the fo??owing inst?uction. [m] [m] C 1 ski? if [m] = 0 none ski? if dec?ement data memo?y is ze?o with ?esu?t in ?cc the contents of the specifed data memory are frst decremented by 1. if the result is 0? the fo?? owing inst? uction is ski?? ed. the ?esu? t is sto? ed in the ?ccumu?ato? but the specifed data memory contents remain unchanged. as this requires the inse? tion of a dummy inst?uction whi? e the next inst? uction is fetched? it is a two cyc? e inst? uction. if the ? esu? t is not 0 ? the ??og? am ?? oceeds with the fo ?? owing inst?uction. ?cc [m] C 1 ski? if ?cc = 0 none rrca [m] desc?i?tion o?e?ation affected fag(s) sbc a,[m] desc?i?tion o?e?ation affected fag(s) sbcm a,[m] desc?i?tion o?e?ation affected fag(s) sdz [m] desc?i?tion o?e?ation affected fag(s) sdza [m] desc?i?tion o?e?ation affected fag(s)
rev 1.00 116 ???i? 1?? ? 011 rev 1.00 117 ???i? 1?? ? 011 HT82A824R usb audio mcu set data memo?y each bit of the specifed data memory is set to 1. [m] ffh none set bit of data memo?y bit i of the specifed data memory is set to 1. [m].1 1 none ski? if inc?ement data memo?y is 0 the contents of the specifed data memory are frst incremented by 1. if the result is 0? the fo?? owing inst? uction is ski??ed. ?s this ?equi? es the inse? tion of a dummy inst?uction whi? e the next inst? uction is fetched? it is a two cyc?e inst? uction. if the ?esu?t is not 0 the ??og?am ??oceeds with the fo??owing inst?uction. [m] [m] + 1 ski? if [m] = 0 none ski? if inc?ement data memo?y is ze?o with ?esu?t in ?cc the contents of the specifed data memory are frst incremented by 1. if the result is 0? the fo??owing inst?uction is ski?? ed. the ?esu?t is sto?ed in the ?ccumu?ato? but the specifed data memory contents remain unchanged. as this requires the inse? tion of a dummy inst? uction whi? e the next inst? uction is fetched? it is a two cyc?e inst? uction. if the ?esu? t is not 0 the ??og?am ?? oceeds with the fo?? owing inst?uction. ?cc [m] + 1 ski? if ?cc = 0 none ski? if bit i of data memo?y is not 0 if bit i of the specifed data memory is not 0, the following instruction is skipped. ?s this ?equi?es the inse?tion of a dummy inst?uction whi?e the next inst?uction is fetched? it is a two cyc? e inst? uction. if the ?esu? t is 0 the ??og?am ?? oceeds with the fo??owing inst?uction. skip if [m].i 0 none subt?act data memo?y f?om ?cc the specifed data memory is subtracted from the contents of the accumulator. the ? esu? t is sto ? ed in the ? ccumu ? ato ? . note that if the ? esu? t of subt ? action is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. ?cc ?cc C [m] ov ? z? ?c? c set [m] desc?i?tion o?e?ation affected fag(s) set [m].i desc?i?tion o?e?ation affected fag(s) siz [m] desc?i?tion o?e?ation affected fag(s) siza [m] desc?i?tion o?e?ation affected fag(s) snz [m].i desc?i?tion o?e?ation affected fag(s) sub a,[m] desc?i?tion o?e?ation affected fag(s)
rev 1.00 118 ???i? 1?? ? 011 rev 1.00 119 ???i? 1?? ? 011 HT82A824R usb audio mcu subt?act data memo?y f?om ?cc with ?esu?t in data memo?y the specifed data memory is subtracted from the contents of the accumulator. the ?esu?t is sto? ed in the data memo? y. note that if the ?esu?t of subt? action is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. [m] ?cc C [m] ov ? z? ?c? c subt?act immediate data f?om ?cc the immediate data specifed by the code is subtracted from the contents of the ? ccumu ? ato? . the ? esu? t is sto? ed in the ? ccumu ? ato? . note that if the ? esu? t of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. ?cc ?cc C x ov ? z? ?c? c swa? nibb?es of data memo?y the ?ow-o?de? and high-o?de? nibb? es of the s? ecified data memo? y a? e inte?changed. [m].3~[m].0?[m].7 ~ [m].4 none swa? nibb?es of data memo?y with ?esu?t in ?cc the ?ow-o?de? and high-o?de? nibb? es of the s? ecified data memo? y a? e inte ? changed. the ?esu? t is sto?ed in the ?ccumu?ato? . the contents of the data memo?y ?emain unchanged. ? cc.3 ~ ?cc.0 [m].7 ~ [m].? ? cc.7 ~ ?cc.? [m].3 ~ [m].0 none ski? if data memo?y is 0 if the contents of the s ? ecified data memo?y is 0? the fo ??owing inst ? uction is ski??ed. ?s this ?equi?es the inse?tion of a dummy inst?uction whi? e the next inst?uction is fetched? it is a two cyc?e inst?uction. if the ?esu?t is not 0 the ??og?am ??oceeds with the fo??owing inst?uction. ski? if [m] = 0 none ski? if data memo?y is 0 with data movement to ?cc the contents of the specifed data memory are copied to the accumulator. if the va? ue is ze?o? the fo?? owing inst? uction is ski??ed. ?s this ?equi? es the inse? tion of a dummy inst?uction whi? e the next inst? uction is fetched? it is a two cyc?e inst?uction. if the ?esu?t is not 0 the ??og?am ??oceeds with the fo??owing inst?uction. ?cc [m] ski? if [m] = 0 none subm a,[m] desc?i?tion o?e?ation affected fag(s) sub a,x desc?i?tion o?e?ation affected fag(s) swap [m] desc?i?tion o?e?ation affected fag(s) swapa [m] desc?i?tion o?e?ation affected fag(s) sz [m] desc?i?tion o?e?ation affected fag(s) sza [m] desc?i?tion o?e?ation affected fag(s)
rev 1.00 118 ???i? 1?? ? 011 rev 1.00 119 ???i? 1?? ? 011 HT82A824R usb audio mcu ski? if bit i of data memo?y is 0 if bit i of the specifed data memory is 0, the following instruction is skipped. as this ?equi? es the inse? tion of a dummy inst ? uction whi? e the next inst ? uction is fetched? it is a two cyc?e inst?uction. if the ?esu?t is not 0? the ??og?am ?? oceeds with the fo??owing inst?uction. ski? if [m].i = 0 none read tab?e (cu??ent ? age) to tblh and data memo?y the ?ow byte of the ??og?am code (cu??ent ?age) add?essed by the tab?e ?ointe? (tblp) is moved to the specifed data memory and the high byte moved to tblh. [m] ??og?am code (?ow byte) tblh ??og?am code (high byte) none read tab?e (?ast ? age) to tblh and data memo?y the ? ow byte of the ?? og? am code ( ? ast ? age) add? essed by the tab ?e ? ointe? (tblp) is moved to the specifed data memory and the high byte moved to tblh. [m] ??og?am code (?ow byte) tblh ??og?am code (high byte) none logica? xor data memo?y to ?cc data in the accumulator and the specifed data memory perform a bitwise logical xor o?e? ation. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc " xor " [m] z logica? xor ?cc to data memo?y data in the specifed data memory and the accumulator perform a bitwise logical xor o?e? ation. the ?esu?t is sto?ed in the data memo? y. [m] ?cc " xor " [m] z logica? xor immediate data to ?cc data in the ?ccumu?ato? and the s?ecified immediate data ?e?fo? m a bitwise ?ogica? xor o?e? ation. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc " xor " x z sz [m].i desc?i?tion o?e?ation affected fag(s) tabrdc [m] desc?i?tion o?e?ation affected fag(s) tabrdl [m] desc?i?tion o?e?ation affected fag(s) xor a,[m] desc?i?tion o?e?ation affected fag(s) xorm a,[m] desc?i?tion o?e?ation affected fag(s) xor a,x desc?i?tion o?e?ation affected fag(s)
rev 1.00 1?0 ???i? 1?? ? 011 rev 1.00 1?1 ???i? 1?? ? 011 HT82A824R usb audio mcu package information 48-pin lqfp (7mmx7mm) outline dimensions 48-pin lqfp (7mm 7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.350 0.358 b 0.272 0.280 c 0.350 0.358 d 0.272 0.280 e 0.020 f 0.008 g 0.053 0.057 h 0.063 i 0.004 j 0.018 0.030 k 0.004 0.008 07 symbol dimensions in mm min. nom. max. a 8.90 9.10 b 6.90 7.10 c 8.90 9.10 d 6.90 7.10 e 0.50 f 0.20 g 1.35 1.45 h 1.60 i 0.10 j 0.45 0.75 k 0.10 0.20 07 package information 1 may 12, 2010 symbol dimensions in inch min. nom. max. ? 0.350 D 0.358 b 0.?7? D 0.?80 c 0.350 D 0.358 d 0.?7? D 0.?80 e D 0.0?0 D f D 0.008 D g 0.053 D 0.057 h D D 0.063 i D 0.00? j 0.018 D 0.030 k 0.00? D 0.008 0 D 7 symbol dimensions in mm min. nom. max. ? 8.90 D 9.10 b 6.90 D 7.10 c 8.90 D 9.10 d 6.90 D 7.10 e D 0.50 D f D 0.?0 D g 1.35 D 1.?5 h D D 1.60 i 0.10 j 0.?5 D 0.75 k 0.10 D 0.?0 0 D 7
rev 1.00 1?0 ???i? 1?? ? 011 rev 1.00 1?1 ???i? 1?? ? 011 HT82A824R usb audio mcu holtek semiconductor inc. (headquarters) no.3? c?eation rd. ii? science pa?k? hsinchu? taiwan te ?: 886-3-563-1999 fax: 886-3-563-1189 htt? ://www.ho?tek.com.tw holtek semiconductor inc. (taipei sales offce) ?f-?? no. 3-?? yuanqu st.? nankang softwa?e pa?k? tai? ei 115? taiwan te ?: 886-?-?655-7070 fax: 886-?-?655-7373 fax: 886-?-?655-7383 (inte?nationa? sa?es hot?ine) holtek semiconductor inc. (shenzhen sales offce) 5f ? unit ?? p?oductivity bui?ding? no.5 gaoxin m ?nd road? nanshan dist?ict? shenzhen? china 518057 te ?: 86-755-8616-9908? 86-755-8616-9308 fax: 86-755-8616-97?? holtek semiconductor (usa), inc. (north america sales offce) ?67?9 f?emont b?vd.? f?emont? c? 9?538? us? te ?: 1-510-?5?-9880 fax: 1-510-?5?-9885 htt? ://www.ho?tek.com co?y?ight ? ? 011 by holtek semiconductor inc. the info?mation a??ea? ing in this data sheet is be? ieved to be accu? ate at the time of ?ub? ication. howeve ?? ho? tek assumes no ?es?onsibi? ity a?ising f ? om the use of the s ? ecifications desc? ibed. the a??? ications mentioned he ? ein a? e used so?e? y fo? the ?u?? ose of i??ust? ation and ho? tek makes no wa?? anty o? representation that such applications will be suitable without further modifcation, nor recommends the use of its ?? oducts fo? a??? ication that may ??esent a ? isk to human ? ife due to ma?function o? othe?wise. ho?tek's ??oducts a?e not autho? ized fo? use as c?itica? com?onents in ?ife su??o?t devices o? systems. ho?tek ?ese?ves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at htt? ://www.ho? tek.com.tw.

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